Commit 7fbb58a0 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus 

Pull MIPS fixes from Ralf Baechle:
 "A fair number of 4.2 fixes also because Markos opened the flood gates.

   - Patch up the math used calculate the location for the page bitmap.

   - The FDC (Not what you think, FDC stands for Fast Debug Channel) IRQ
     around was causing issues on non-Malta platforms, so move the code
     to a Malta specific location.

   - A spelling fix replicated through several files.

   - Fix to the emulation of an R2 instruction for R6 cores.

   - Fix the JR emulation for R6.

   - Further patching of mindless 64 bit issues.

   - Ensure the kernel won't crash on CPUs with L2 caches with >= 8
     ways.

   - Use compat_sys_getsockopt for O32 ABI on 64 bit kernels.

   - Fix cache flushing for multithreaded cores.

   - A build fix"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
  MIPS: O32: Use compat_sys_getsockopt.
  MIPS: c-r4k: Extend way_string array
  MIPS: Pistachio: Support CDMM & Fast Debug Channel
  MIPS: Malta: Make GIC FDC IRQ workaround Malta specific
  MIPS: c-r4k: Fix cache flushing for MT cores
  Revert "MIPS: Kconfig: Disable SMP/CPS for 64-bit"
  MIPS: cps-vec: Use macros for various arithmetics and memory operations
  MIPS: kernel: cps-vec: Replace KSEG0 with CKSEG0
  MIPS: kernel: cps-vec: Use ta0-ta3 pseudo-registers for 64-bit
  MIPS: kernel: cps-vec: Replace mips32r2 ISA level with mips64r2
  MIPS: kernel: cps-vec: Replace 'la' macro with PTR_LA
  MIPS: kernel: smp-cps: Fix 64-bit compatibility errors due to pointer casting
  MIPS: Fix erroneous JR emulation for MIPS R6
  MIPS: Fix branch emulation for BLTC and BGEC instructions
  MIPS: kernel: traps: Fix broken indentation
  MIPS: bootmem: Don't use memory holes for page bitmap
  MIPS: O32: Do not handle require 32 bytes from the stack to be readable.
  MIPS, CPUFREQ: Fix spelling of Institute.
  MIPS: Lemote 2F: Fix build caused by recent mass rename.
parents 1daa1cfb 51d53674

arch/mips/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -2231,7 +2231,7 @@ config MIPS_CMP 


config MIPS_CPS

	bool "MIPS Coherent Processing System support"

	depends on SYS_SUPPORTS_MIPS_CPS && !64BIT

	depends on SYS_SUPPORTS_MIPS_CPS

	select MIPS_CM

	select MIPS_CPC

	select MIPS_CPS_PM if HOTPLUG_CPU

arch/mips/include/asm/mach-loongson64/mmzone.h

+1 −1
Original line number Diff line number Diff line 
/*

 * Copyright (C) 2010 Loongson Inc. & Lemote Inc. &

 *                    Insititute of Computing Technology

 *                    Institute of Computing Technology

 * Author:  Xiang Gao, gaoxiang@ict.ac.cn

 *          Huacai Chen, chenhc@lemote.com

 *          Xiaofu Meng, Shuangshuang Zhang

arch/mips/include/asm/smp.h

+1 −0
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ 
extern int smp_num_siblings;

extern cpumask_t cpu_sibling_map[];

extern cpumask_t cpu_core_map[];

extern cpumask_t cpu_foreign_map;



#define raw_smp_processor_id() (current_thread_info()->cpu)

arch/mips/kernel/branch.c

+2 −2
Original line number Diff line number Diff line
@@ -600,7 +600,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs, 
		break;



	case blezl_op: /* not really i_format */

		if (NO_R6EMU)

		if (!insn.i_format.rt && NO_R6EMU)

			goto sigill_r6;

	case blez_op:

		/*
@@ -635,7 +635,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs, 
		break;



	case bgtzl_op:

		if (NO_R6EMU)

		if (!insn.i_format.rt && NO_R6EMU)

			goto sigill_r6;

	case bgtz_op:

		/*

arch/mips/kernel/cps-vec.S

+48 −48
Original line number Diff line number Diff line
@@ -60,7 +60,7 @@ LEAF(mips_cps_core_entry) 
	 nop



	/* This is an NMI */

	la	k0, nmi_handler

	PTR_LA	k0, nmi_handler

	jr	k0

	 nop
@@ -107,10 +107,10 @@ not_nmi: 
	mul	t1, t1, t0

	mul	t1, t1, t2



	li	a0, KSEG0

	add	a1, a0, t1

	li	a0, CKSEG0

	PTR_ADD	a1, a0, t1

1:	cache	Index_Store_Tag_I, 0(a0)

	add	a0, a0, t0

	PTR_ADD	a0, a0, t0

	bne	a0, a1, 1b

	 nop

icache_done:
@@ -134,12 +134,12 @@ icache_done: 
	mul	t1, t1, t0

	mul	t1, t1, t2



	li	a0, KSEG0

	addu	a1, a0, t1

	subu	a1, a1, t0

	li	a0, CKSEG0

	PTR_ADDU a1, a0, t1

	PTR_SUBU a1, a1, t0

1:	cache	Index_Store_Tag_D, 0(a0)

	bne	a0, a1, 1b

	 add	a0, a0, t0

	 PTR_ADD a0, a0, t0

dcache_done:



	/* Set Kseg0 CCA to that in s0 */
@@ -152,11 +152,11 @@ dcache_done: 


	/* Enter the coherent domain */

	li	t0, 0xff

	sw	t0, GCR_CL_COHERENCE_OFS(v1)

	PTR_S	t0, GCR_CL_COHERENCE_OFS(v1)

	ehb



	/* Jump to kseg0 */

	la	t0, 1f

	PTR_LA	t0, 1f

	jr	t0

	 nop
@@ -178,9 +178,9 @@ dcache_done: 
	 nop



	/* Off we go! */

	lw	t1, VPEBOOTCFG_PC(v0)

	lw	gp, VPEBOOTCFG_GP(v0)

	lw	sp, VPEBOOTCFG_SP(v0)

	PTR_L	t1, VPEBOOTCFG_PC(v0)

	PTR_L	gp, VPEBOOTCFG_GP(v0)

	PTR_L	sp, VPEBOOTCFG_SP(v0)

	jr	t1

	 nop

	END(mips_cps_core_entry)
@@ -217,7 +217,7 @@ LEAF(excep_intex) 


.org 0x480

LEAF(excep_ejtag)

	la	k0, ejtag_debug_handler

	PTR_LA	k0, ejtag_debug_handler

	jr	k0

	 nop

	END(excep_ejtag)
@@ -229,7 +229,7 @@ LEAF(mips_cps_core_init) 
	 nop



	.set	push

	.set	mips32r2

	.set	mips64r2

	.set	mt



	/* Only allow 1 TC per VPE to execute... */
@@ -237,7 +237,7 @@ LEAF(mips_cps_core_init) 


	/* ...and for the moment only 1 VPE */

	dvpe

	la	t1, 1f

	PTR_LA	t1, 1f

	jr.hb	t1

	 nop
@@ -250,25 +250,25 @@ LEAF(mips_cps_core_init) 
	mfc0	t0, CP0_MVPCONF0

	srl	t0, t0, MVPCONF0_PVPE_SHIFT

	andi	t0, t0, (MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT)

	addiu	t7, t0, 1

	addiu	ta3, t0, 1



	/* If there's only 1, we're done */

	beqz	t0, 2f

	 nop



	/* Loop through each VPE within this core */

	li	t5, 1

	li	ta1, 1



1:	/* Operate on the appropriate TC */

	mtc0	t5, CP0_VPECONTROL

	mtc0	ta1, CP0_VPECONTROL

	ehb



	/* Bind TC to VPE (1:1 TC:VPE mapping) */

	mttc0	t5, CP0_TCBIND

	mttc0	ta1, CP0_TCBIND



	/* Set exclusive TC, non-active, master */

	li	t0, VPECONF0_MVP

	sll	t1, t5, VPECONF0_XTC_SHIFT

	sll	t1, ta1, VPECONF0_XTC_SHIFT

	or	t0, t0, t1

	mttc0	t0, CP0_VPECONF0
@@ -280,8 +280,8 @@ LEAF(mips_cps_core_init) 
	mttc0	t0, CP0_TCHALT



	/* Next VPE */

	addiu	t5, t5, 1

	slt	t0, t5, t7

	addiu	ta1, ta1, 1

	slt	t0, ta1, ta3

	bnez	t0, 1b

	 nop
@@ -298,19 +298,19 @@ LEAF(mips_cps_core_init) 


LEAF(mips_cps_boot_vpes)

	/* Retrieve CM base address */

	la	t0, mips_cm_base

	lw	t0, 0(t0)

	PTR_LA	t0, mips_cm_base

	PTR_L	t0, 0(t0)



	/* Calculate a pointer to this cores struct core_boot_config */

	lw	t0, GCR_CL_ID_OFS(t0)

	PTR_L	t0, GCR_CL_ID_OFS(t0)

	li	t1, COREBOOTCFG_SIZE

	mul	t0, t0, t1

	la	t1, mips_cps_core_bootcfg

	lw	t1, 0(t1)

	addu	t0, t0, t1

	PTR_LA	t1, mips_cps_core_bootcfg

	PTR_L	t1, 0(t1)

	PTR_ADDU t0, t0, t1



	/* Calculate this VPEs ID. If the core doesn't support MT use 0 */

	has_mt	t6, 1f

	has_mt	ta2, 1f

	 li	t9, 0



	/* Find the number of VPEs present in the core */
@@ -334,24 +334,24 @@ LEAF(mips_cps_boot_vpes) 
1:	/* Calculate a pointer to this VPEs struct vpe_boot_config */

	li	t1, VPEBOOTCFG_SIZE

	mul	v0, t9, t1

	lw	t7, COREBOOTCFG_VPECONFIG(t0)

	addu	v0, v0, t7

	PTR_L	ta3, COREBOOTCFG_VPECONFIG(t0)

	PTR_ADDU v0, v0, ta3



#ifdef CONFIG_MIPS_MT



	/* If the core doesn't support MT then return */

	bnez	t6, 1f

	bnez	ta2, 1f

	 nop

	jr	ra

	 nop



	.set	push

	.set	mips32r2

	.set	mips64r2

	.set	mt



1:	/* Enter VPE configuration state */

	dvpe

	la	t1, 1f

	PTR_LA	t1, 1f

	jr.hb	t1

	 nop

1:	mfc0	t1, CP0_MVPCONTROL
@@ -360,12 +360,12 @@ LEAF(mips_cps_boot_vpes) 
	ehb



	/* Loop through each VPE */

	lw	t6, COREBOOTCFG_VPEMASK(t0)

	move	t8, t6

	li	t5, 0

	PTR_L	ta2, COREBOOTCFG_VPEMASK(t0)

	move	t8, ta2

	li	ta1, 0



	/* Check whether the VPE should be running. If not, skip it */

1:	andi	t0, t6, 1

1:	andi	t0, ta2, 1

	beqz	t0, 2f

	 nop
@@ -373,7 +373,7 @@ LEAF(mips_cps_boot_vpes) 
	mfc0	t0, CP0_VPECONTROL

	ori	t0, t0, VPECONTROL_TARGTC

	xori	t0, t0, VPECONTROL_TARGTC

	or	t0, t0, t5

	or	t0, t0, ta1

	mtc0	t0, CP0_VPECONTROL

	ehb
@@ -384,8 +384,8 @@ LEAF(mips_cps_boot_vpes) 


	/* Calculate a pointer to the VPEs struct vpe_boot_config */

	li	t0, VPEBOOTCFG_SIZE

	mul	t0, t0, t5

	addu	t0, t0, t7

	mul	t0, t0, ta1

	addu	t0, t0, ta3



	/* Set the TC restart PC */

	lw	t1, VPEBOOTCFG_PC(t0)
@@ -423,9 +423,9 @@ LEAF(mips_cps_boot_vpes) 
	mttc0	t0, CP0_VPECONF0



	/* Next VPE */

2:	srl	t6, t6, 1

	addiu	t5, t5, 1

	bnez	t6, 1b

2:	srl	ta2, ta2, 1

	addiu	ta1, ta1, 1

	bnez	ta2, 1b

	 nop



	/* Leave VPE configuration state */
@@ -445,7 +445,7 @@ LEAF(mips_cps_boot_vpes) 
	/* This VPE should be offline, halt the TC */

	li	t0, TCHALT_H

	mtc0	t0, CP0_TCHALT

	la	t0, 1f

	PTR_LA	t0, 1f

1:	jr.hb	t0

	 nop
@@ -466,10 +466,10 @@ LEAF(mips_cps_boot_vpes) 
	.set	noat

	lw	$1, TI_CPU(gp)

	sll	$1, $1, LONGLOG

	la	\dest, __per_cpu_offset

	PTR_LA	\dest, __per_cpu_offset

	addu	$1, $1, \dest

	lw	$1, 0($1)

	la	\dest, cps_cpu_state

	PTR_LA	\dest, cps_cpu_state

	addu	\dest, \dest, $1

	.set	pop

	.endm

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