qlcnic: 83xx memory map and HW access routines

qlcnic-y := qlcnic_hw.o qlcnic_main.o qlcnic_init.o \

	qlcnic_ethtool.o qlcnic_ctx.o qlcnic_io.o \

	qlcnic_sysfs.o qlcnic_minidump.o

	qlcnic_sysfs.o qlcnic_minidump.o qlcnic_83xx_hw.o

#include <linux/if_vlan.h>

#include "qlcnic_hdr.h"

#include "qlcnic_hw.h"

#include "qlcnic_83xx_hw.h"

#define _QLCNIC_LINUX_MAJOR 5

#define _QLCNIC_LINUX_MINOR 0

#define TX_STOP_THRESH		((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \

							+ MGMT_CMD_DESC_RESV)

#define QLCNIC_MAX_TX_TIMEOUTS	2

/*

 * Following are the states of the Phantom. Phantom will set them and

 * Host will read to check if the fields are correct.

	u32 temp;

	u32 int_vec_bit;

	u32 fw_hal_version;

	u32 port_config;

	struct qlcnic_hardware_ops *hw_ops;

	struct qlcnic_nic_intr_coalesce coal;

	struct qlcnic_fw_dump fw_dump;

	struct qlcnic_intrpt_config *intr_tbl;

	u32 *reg_tbl;

	u32 *ext_reg_tbl;

	u32 mbox_aen[QLC_83XX_MBX_AEN_CNT];

	u32 mbox_reg[4];

	spinlock_t mbx_lock;

};

struct qlcnic_adapter_stats {

	u64  null_rxbuf;

	u64  rx_dma_map_error;

	u64  tx_dma_map_error;

	u64  spurious_intr;

};

/*

} ____cacheline_internodealigned_in_smp;

struct qlcnic_host_tx_ring {

	void __iomem *crb_intr_mask;

	char name[IFNAMSIZ+4];

	u16 ctx_id;

	u32 producer;

	u32 sw_consumer;

 */

#define QLCNIC_C2H_OPCODE_CONFIG_LOOPBACK		0x8f

#define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE	141

#define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE	0x8D

#define VPORT_MISS_MODE_DROP		0 /* drop all unmatched */

#define VPORT_MISS_MODE_ACCEPT_ALL	1 /* accept all packets */

#define QLCNIC_MSI_ENABLED		0x02

#define QLCNIC_MSIX_ENABLED		0x04

#define QLCNIC_LRO_ENABLED		0x08

#define QLCNIC_LRO_ENABLED		0x01

#define QLCNIC_LRO_DISABLED		0x00

#define QLCNIC_BRIDGE_ENABLED       	0X10

#define QLCNIC_DIAG_ENABLED		0x20

#define QLCNIC_FILTER_AGE	80

#define QLCNIC_READD_AGE	20

#define QLCNIC_LB_MAX_FILTERS	64

#define QLCNIC_LB_BUCKET_SIZE	32

/* QLCNIC Driver Error Code */

#define QLCNIC_FW_NOT_RESPOND		51

struct qlcnic_filter_hash {

	struct hlist_head *fhead;

	u8 fnum;

	u8 fmax;

	u16 fmax;

	u16 fbucket_size;

};

struct qlcnic_adapter {

	u8 max_rds_rings;

	u8 max_sds_rings;

	u8 rx_csum;

	u8 portnum;

	u8 fw_wait_cnt;

	void __iomem	*isr_int_vec;

	struct msix_entry *msix_entries;

	struct workqueue_struct *qlcnic_wq;

	struct delayed_work fw_work;

	struct delayed_work idc_aen_work;

	struct qlcnic_filter_hash fhash;

	__le16	max_rx_ques;

	__le16	min_tx_bw;

	__le16	max_tx_bw;

	u8	reserved2[104];

	__le32  op_type;

	__le16  max_bw_reg_offset;

	__le16  max_linkspeed_reg_offset;

	__le32  capability1;

	__le32  capability2;

	__le32  capability3;

	__le16  max_tx_mac_filters;

	__le16  max_rx_mcast_mac_filters;

	__le16  max_rx_ucast_mac_filters;

	__le16  max_rx_ip_addr;

	__le16  max_rx_lro_flow;

	__le16  max_rx_status_rings;

	__le16  max_rx_buf_rings;

	__le16  max_tx_vlan_keys;

	u8      total_pf;

	u8      total_rss_engines;

	__le16  max_vports;

	u8      reserved2[64];

} __packed;

struct qlcnic_info {

	u16	max_rx_ques;

	u16	min_tx_bw;

	u16	max_tx_bw;

	u32	op_type;

	u16	max_bw_reg_offset;

	u16	max_linkspeed_reg_offset;

	u32	capability1;

	u32	capability2;

	u32	capability3;

	u16	max_tx_mac_filters;

	u16	max_rx_mcast_mac_filters;

	u16	max_rx_ucast_mac_filters;

	u16	max_rx_ip_addr;

	u16	max_rx_lro_flow;

	u16	max_rx_status_rings;

	u16	max_rx_buf_rings;

	u16	max_tx_vlan_keys;

	u8      total_pf;

	u8      total_rss_engines;

	u16	max_vports;

};

struct qlcnic_pci_info_le {

	__le16	reserved1[2];

	u8	mac[ETH_ALEN];

	u8	reserved2[106];

	__le16  func_count;

	u8      reserved2[104];

} __packed;

struct qlcnic_pci_info {

	u16	tx_min_bw;

	u16	tx_max_bw;

	u8	mac[ETH_ALEN];

	u16  func_count;

};

struct qlcnic_npar_info {

int qlcnic_set_max_rss(struct qlcnic_adapter *adapter, u8 data);

int qlcnic_validate_max_rss(struct net_device *netdev, u8, u8);

void qlcnic_alloc_lb_filters_mem(struct qlcnic_adapter *adapter);

int qlcnic_enable_msix(struct qlcnic_adapter *, u32);

/*  eSwitch management functions */

int qlcnic_config_switch_port(struct qlcnic_adapter *,

int qlcnic_alloc_sds_rings(struct qlcnic_recv_context *, int);

void qlcnic_free_sds_rings(struct qlcnic_recv_context *);

void qlcnic_advert_link_change(struct qlcnic_adapter *, int);

void qlcnic_free_tx_rings(struct qlcnic_adapter *);

int qlcnic_alloc_tx_rings(struct qlcnic_adapter *, struct net_device *);

	adapter->ahw->hw_ops->write_crb(adapter, buf, offset, size);

}

static inline u32 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter,

static inline int qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter,

				       ulong off)

{

	return adapter->ahw->hw_ops->read_reg(adapter, off);

			__func__, ##_args);		\

	} while (0)

#define PCI_DEVICE_ID_QLOGIC_QLE834X    0x8030

#define PCI_DEVICE_ID_QLOGIC_QLE824X	0x8020

static inline bool qlcnic_82xx_check(struct qlcnic_adapter *adapter)

{

	return (device == PCI_DEVICE_ID_QLOGIC_QLE824X) ? true : false;

}

static inline bool qlcnic_83xx_check(struct qlcnic_adapter *adapter)

{

	unsigned short device = adapter->pdev->device;

	return (device == PCI_DEVICE_ID_QLOGIC_QLE834X) ? true : false;

}

#endif				/* __QLCNIC_H_ */

#ifndef __QLCNIC_83XX_HW_H

#define __QLCNIC_83XX_HW_H

#include <linux/types.h>

#include <linux/etherdevice.h>

#include "qlcnic_hw.h"

/* Directly mapped registers */

#define QLC_83XX_CRB_WIN_BASE		0x3800

#define QLC_83XX_CRB_WIN_FUNC(f)	(QLC_83XX_CRB_WIN_BASE+((f)*4))

#define QLC_83XX_SEM_LOCK_BASE		0x3840

#define QLC_83XX_SEM_UNLOCK_BASE	0x3844

#define QLC_83XX_SEM_LOCK_FUNC(f)	(QLC_83XX_SEM_LOCK_BASE+((f)*8))

#define QLC_83XX_SEM_UNLOCK_FUNC(f)	(QLC_83XX_SEM_UNLOCK_BASE+((f)*8))

#define QLC_83XX_LINK_STATE(f)		(0x3698+((f) > 7 ? 4 : 0))

#define QLC_83XX_LINK_SPEED(f)		(0x36E0+(((f) >> 2) * 4))

#define QLC_83XX_LINK_SPEED_FACTOR	10

#define QLC_83xx_FUNC_VAL(v, f)	((v) & (1 << (f * 4)))

#define QLC_83XX_INTX_PTR		0x38C0

#define QLC_83XX_INTX_TRGR		0x38C4

#define QLC_83XX_INTX_MASK		0x38C8

#define QLC_83XX_DRV_LOCK_WAIT_COUNTER			100

#define QLC_83XX_DRV_LOCK_WAIT_DELAY			20

#define QLC_83XX_NEED_DRV_LOCK_RECOVERY		1

#define QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS		2

#define QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT		3

#define QLC_83XX_DRV_LOCK_RECOVERY_DELAY		200

#define QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK		0x3

#define QLC_83XX_NO_NIC_RESOURCE	0x5

#define QLC_83XX_MAC_PRESENT		0xC

#define QLC_83XX_MAC_ABSENT		0xD

#define QLC_83XX_FLASH_SECTOR_SIZE		(64 * 1024)

/* PEG status definitions */

#define QLC_83XX_CMDPEG_COMPLETE		0xff01

#define QLC_83XX_VALID_INTX_BIT30(val)		((val) & BIT_30)

#define QLC_83XX_VALID_INTX_BIT31(val)		((val) & BIT_31)

#define QLC_83XX_INTX_FUNC(val)		((val) & 0xFF)

#define QLC_83XX_LEGACY_INTX_MAX_RETRY		100

#define QLC_83XX_LEGACY_INTX_DELAY		4

#define QLC_83XX_REG_DESC			1

#define QLC_83XX_LRO_DESC			2

#define QLC_83XX_CTRL_DESC			3

#define QLC_83XX_FW_CAPABILITY_TSO		BIT_6

#define QLC_83XX_FW_CAP_LRO_MSS		BIT_17

#define QLC_83XX_HOST_RDS_MODE_UNIQUE		0

#define QLC_83XX_HOST_SDS_MBX_IDX		8

#define QLCNIC_HOST_RDS_MBX_IDX			88

#define QLCNIC_MAX_RING_SETS			8

struct qlcnic_intrpt_config {

	u8	type;

	u8	enabled;

	u16	id;

	u32	src;

};

struct qlcnic_macvlan_mbx {

	u8	mac[ETH_ALEN];

	u16	vlan;

};

/* Mailbox process AEN count */

#define QLC_83XX_IDC_COMP_AEN			3

#define QLC_83XX_MBX_AEN_CNT			5

#define QLC_83XX_MODULE_LOADED			1

#define QLC_83XX_MBX_READY			2

#define QLC_83XX_MBX_AEN_ACK			3

#define QLC_83XX_SFP_PRESENT(data)		((data) & 3)

#define QLC_83XX_SFP_ERR(data)			(((data) >> 2) & 3)

#define QLC_83XX_SFP_MODULE_TYPE(data)		(((data) >> 4) & 0x1F)

#define QLC_83XX_SFP_CU_LENGTH(data)		(LSB((data) >> 16))

#define QLC_83XX_SFP_TX_FAULT(data)		((data) & BIT_10)

#define QLC_83XX_SFP_10G_CAPABLE(data)		((data) & BIT_11)

#define QLC_83XX_LINK_STATS(data)		((data) & BIT_0)

#define QLC_83XX_CURRENT_LINK_SPEED(data)	(((data) >> 3) & 7)

#define QLC_83XX_LINK_PAUSE(data)		(((data) >> 6) & 3)

#define QLC_83XX_LINK_LB(data)			(((data) >> 8) & 7)

#define QLC_83XX_LINK_FEC(data)		((data) & BIT_12)

#define QLC_83XX_LINK_EEE(data)		((data) & BIT_13)

#define QLC_83XX_DCBX(data)			(((data) >> 28) & 7)

#define QLC_83XX_AUTONEG(data)			((data) & BIT_15)

#define QLC_83XX_CFG_STD_PAUSE			(1 << 5)

#define QLC_83XX_CFG_STD_TX_PAUSE		(1 << 20)

#define QLC_83XX_CFG_STD_RX_PAUSE		(2 << 20)

#define QLC_83XX_CFG_STD_TX_RX_PAUSE		(3 << 20)

#define QLC_83XX_ENABLE_AUTONEG		(1 << 15)

#define QLC_83XX_CFG_LOOPBACK_HSS		(2 << 1)

#define QLC_83XX_CFG_LOOPBACK_PHY		(3 << 1)

#define QLC_83XX_CFG_LOOPBACK_EXT		(4 << 1)

/* LED configuration settings */

#define QLC_83XX_ENABLE_BEACON		0xe

#define QLC_83XX_LED_RATE		0xff

#define QLC_83XX_LED_ACT		(1 << 10)

#define QLC_83XX_LED_MOD		(0 << 13)

#define QLC_83XX_LED_CONFIG	(QLC_83XX_LED_RATE | QLC_83XX_LED_ACT |	\

				 QLC_83XX_LED_MOD)

#define QLC_83XX_10M_LINK	1

#define QLC_83XX_100M_LINK	2

#define QLC_83XX_1G_LINK	3

#define QLC_83XX_10G_LINK	4

#define QLC_83XX_STAT_TX	3

#define QLC_83XX_STAT_RX	2

#define QLC_83XX_STAT_MAC	1

#define QLC_83XX_TX_STAT_REGS	14

#define QLC_83XX_RX_STAT_REGS	40

#define QLC_83XX_MAC_STAT_REGS	80

#define QLC_83XX_GET_FUNC_PRIVILEGE(VAL, FN)	(0x3 & ((VAL) >> (FN * 2)))

#define QLC_83XX_SET_FUNC_OPMODE(VAL, FN)	((VAL) << (FN * 2))

#define QLC_83XX_DEFAULT_OPMODE			0x55555555

#define QLC_83XX_PRIVLEGED_FUNC			0x1

#define QLC_83XX_VIRTUAL_FUNC				0x2

#define QLC_83XX_LB_MAX_FILTERS			2048

#define QLC_83XX_LB_BUCKET_SIZE			256

#define QLC_83XX_MINIMUM_VECTOR			3

#define QLC_83XX_GET_FUNC_MODE_FROM_NPAR_INFO(val)	(val & 0x80000000)

#define QLC_83XX_GET_LRO_CAPABILITY(val)		(val & 0x20)

#define QLC_83XX_GET_LSO_CAPABILITY(val)		(val & 0x40)

#define QLC_83XX_GET_LSO_CAPABILITY(val)		(val & 0x40)

#define QLC_83XX_GET_HW_LRO_CAPABILITY(val)		(val & 0x400)

#define QLC_83XX_GET_VLAN_ALIGN_CAPABILITY(val)	(val & 0x4000)

#define QLC_83XX_VIRTUAL_NIC_MODE			0xFF

#define QLC_83XX_DEFAULT_MODE				0x0

#define QLCNIC_BRDTYPE_83XX_10G			0x0083

/* Additional registers in 83xx */

enum qlc_83xx_ext_regs {

	QLCNIC_GLOBAL_RESET = 0,

	QLCNIC_WILDCARD,

	QLCNIC_INFORMANT,

	QLCNIC_HOST_MBX_CTRL,

	QLCNIC_FW_MBX_CTRL,

	QLCNIC_BOOTLOADER_ADDR,

	QLCNIC_BOOTLOADER_SIZE,

	QLCNIC_FW_IMAGE_ADDR,

	QLCNIC_MBX_INTR_ENBL,

	QLCNIC_DEF_INT_MASK,

	QLCNIC_DEF_INT_ID,

	QLC_83XX_IDC_MAJ_VERSION,

	QLC_83XX_IDC_DEV_STATE,

	QLC_83XX_IDC_DRV_PRESENCE,

	QLC_83XX_IDC_DRV_ACK,

	QLC_83XX_IDC_CTRL,

	QLC_83XX_IDC_DRV_AUDIT,

	QLC_83XX_IDC_MIN_VERSION,

	QLC_83XX_RECOVER_DRV_LOCK,

	QLC_83XX_IDC_PF_0,

	QLC_83XX_IDC_PF_1,

	QLC_83XX_IDC_PF_2,

	QLC_83XX_IDC_PF_3,

	QLC_83XX_IDC_PF_4,

	QLC_83XX_IDC_PF_5,

	QLC_83XX_IDC_PF_6,

	QLC_83XX_IDC_PF_7,

	QLC_83XX_IDC_PF_8,

	QLC_83XX_IDC_PF_9,

	QLC_83XX_IDC_PF_10,

	QLC_83XX_IDC_PF_11,

	QLC_83XX_IDC_PF_12,

	QLC_83XX_IDC_PF_13,

	QLC_83XX_IDC_PF_14,

	QLC_83XX_IDC_PF_15,

	QLC_83XX_IDC_DEV_PARTITION_INFO_1,

	QLC_83XX_IDC_DEV_PARTITION_INFO_2,

	QLC_83XX_DRV_OP_MODE,

	QLC_83XX_VNIC_STATE,

	QLC_83XX_DRV_LOCK,

	QLC_83XX_DRV_UNLOCK,

	QLC_83XX_DRV_LOCK_ID,

	QLC_83XX_ASIC_TEMP,

};

/* 83xx funcitons */

int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *);

int qlcnic_83xx_mbx_op(struct qlcnic_adapter *, struct qlcnic_cmd_args *);

int qlcnic_83xx_setup_intr(struct qlcnic_adapter *, u8);

void qlcnic_83xx_get_func_no(struct qlcnic_adapter *);

int qlcnic_83xx_cam_lock(struct qlcnic_adapter *);

void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *);

int qlcnic_send_ctrl_op(struct qlcnic_adapter *, struct qlcnic_cmd_args *, u32);

void qlcnic_83xx_write_crb(struct qlcnic_adapter *, char *, loff_t, size_t);

void qlcnic_83xx_read_crb(struct qlcnic_adapter *, char *, loff_t, size_t);

int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *, ulong);

int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *, ulong, u32);

void qlcnic_83xx_process_rcv_diag(struct qlcnic_adapter *,

				  struct qlcnic_host_sds_ring *, int, u64 []);

int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *, u32);

int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *, u8);

int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *, u8);

int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *, int);

int qlcnic_83xx_config_rss(struct qlcnic_adapter *, int);

int qlcnic_83xx_config_intr_coalesce(struct qlcnic_adapter *);

void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *, u64 *, __le16);

int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info *);

int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *);

void qlcnic_83xx_register_nic_idc_func(struct qlcnic_adapter *, int);

void qlcnic_ind_wr(struct qlcnic_adapter *, u32, u32);

int qlcnic_ind_rd(struct qlcnic_adapter *, u32);

void qlcnic_83xx_get_stats(struct qlcnic_adapter *,

			   struct ethtool_stats *, u64 *);

int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *);

int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *,

			      struct qlcnic_host_tx_ring *, int);

int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8);

int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *, int);

void qlcnic_83xx_process_rcv_ring_diag(struct qlcnic_host_sds_ring *);

int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *, bool);

int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *, u8 *, __le16, u8);

int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *, u8 *);

void qlcnic_83xx_configure_mac(struct qlcnic_adapter *, u8 *, u8,

			       struct qlcnic_cmd_args *);

int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *,

			       struct qlcnic_adapter *, u32);

void qlcnic_free_mbx_args(struct qlcnic_cmd_args *);

void qlcnic_set_npar_data(struct qlcnic_adapter *, const struct qlcnic_info *,

			  struct qlcnic_info *);

void qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *);

irqreturn_t qlcnic_83xx_handle_aen(int, void *);

int qlcnic_83xx_get_port_info(struct qlcnic_adapter *);

void qlcnic_83xx_enable_mbx_intrpt(struct qlcnic_adapter *);

irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *);

irqreturn_t qlcnic_83xx_tmp_intr(int, void *);

void qlcnic_83xx_enable_intr(struct qlcnic_adapter *,

			     struct qlcnic_host_sds_ring *);

void qlcnic_83xx_check_vf(struct qlcnic_adapter *,

			  const struct pci_device_id *);

void qlcnic_83xx_process_aen(struct qlcnic_adapter *);

int qlcnic_83xx_get_port_config(struct qlcnic_adapter *);

int qlcnic_83xx_set_port_config(struct qlcnic_adapter *);

int qlcnic_enable_eswitch(struct qlcnic_adapter *, u8, u8);

int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *);

int qlcnic_83xx_config_default_opmode(struct qlcnic_adapter *);

int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *);

void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *);

void qlcnic_83xx_register_map(struct qlcnic_hardware_context *);

void qlcnic_83xx_idc_aen_work(struct work_struct *);

void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *, __be32, int);

#endif

#define QLCNIC_NIU_GB_MAC_CONFIG_1(I)		\

		(QLCNIC_CRB_NIU + 0x30004 + (I)*0x10000)

#define MAX_CTL_CHECK	1000

#define TEST_AGT_CTRL	(0x00)

#define TA_CTL_START	BIT_0

#define QLCNIC_HEARTBEAT_PERIOD_MSECS	200

#define QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT	45

#define QLCNIC_MAX_MC_COUNT		38

#define QLCNIC_WATCHDOG_TIMEOUTVALUE	5

#define	ISR_MSI_INT_TRIGGER(FUNC) (QLCNIC_PCIX_PS_REG(PCIX_MSI_F(FUNC)))

#define ISR_LEGACY_INT_TRIGGERED(VAL)	(((VAL) & 0x300) == 0x200)

enum {

	QLCNIC_MGMT_FUNC	= 0,

	QLCNIC_PRIV_FUNC	= 1,

	QLCNIC_NON_PRIV_FUNC	= 2

	QLCNIC_NON_PRIV_FUNC	= 2,

	QLCNIC_UNKNOWN_FUNC_MODE = 3

};

enum {

#define QLCNIC_NIU_PROMISC_MODE		1

#define QLCNIC_NIU_ALLMULTI_MODE	2

#define QLCNIC_PCIE_SEM_TIMEOUT	10000

struct crb_128M_2M_sub_block_map {

	unsigned valid;

	unsigned start_128M;