Commit 7f8f209f authored by Sinan Kaya's avatar Sinan Kaya Committed by Vinod Koul
Browse files

dmaengine: add Qualcomm Technologies HIDMA management driver 



The Qualcomm Technologies HIDMA device has been designed to support
virtualization technology. The driver has been divided into two to follow
the hardware design.

1. HIDMA Management driver
2. HIDMA Channel driver

Each HIDMA HW consists of multiple channels. These channels share some set
of common parameters. These parameters are initialized by the management
driver during power up. Same management driver is used for monitoring the
execution of the channels. Management driver can change the performance
behavior dynamically such as bandwidth allocation and prioritization.

The management driver is executed in host context and is the main
management entity for all channels provided by the device.

Signed-off-by: default avatarSinan Kaya <okaya@codeaurora.org>
Reviewed-by: default avatarAndy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: default avatarVinod Koul <vinod.koul@intel.com>
parent 858de34c

Documentation/ABI/testing/sysfs-platform-hidma-mgmt

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What:		/sys/devices/platform/hidma-mgmt*/chanops/chan*/priority

		/sys/devices/platform/QCOM8060:*/chanops/chan*/priority

Date:		Nov 2015

KernelVersion:	4.4

Contact:	"Sinan Kaya <okaya@cudeaurora.org>"

Description:

		Contains either 0 or 1 and indicates if the DMA channel is a

		low priority (0) or high priority (1) channel.



What:		/sys/devices/platform/hidma-mgmt*/chanops/chan*/weight

		/sys/devices/platform/QCOM8060:*/chanops/chan*/weight

Date:		Nov 2015

KernelVersion:	4.4

Contact:	"Sinan Kaya <okaya@cudeaurora.org>"

Description:

		Contains 0..15 and indicates the weight of the channel among

		equal priority channels during round robin scheduling.



What:		/sys/devices/platform/hidma-mgmt*/chreset_timeout_cycles

		/sys/devices/platform/QCOM8060:*/chreset_timeout_cycles

Date:		Nov 2015

KernelVersion:	4.4

Contact:	"Sinan Kaya <okaya@cudeaurora.org>"

Description:

		Contains the platform specific cycle value to wait after a

		reset command is issued. If the value is chosen too short,

		then the HW will issue a reset failure interrupt. The value

		is platform specific and should not be changed without

		consultance.



What:		/sys/devices/platform/hidma-mgmt*/dma_channels

		/sys/devices/platform/QCOM8060:*/dma_channels

Date:		Nov 2015

KernelVersion:	4.4

Contact:	"Sinan Kaya <okaya@cudeaurora.org>"

Description:

		Contains the number of dma channels supported by one instance

		of HIDMA hardware. The value may change from chip to chip.



What:		/sys/devices/platform/hidma-mgmt*/hw_version_major

		/sys/devices/platform/QCOM8060:*/hw_version_major

Date:		Nov 2015

KernelVersion:	4.4

Contact:	"Sinan Kaya <okaya@cudeaurora.org>"

Description:

		Version number major for the hardware.



What:		/sys/devices/platform/hidma-mgmt*/hw_version_minor

		/sys/devices/platform/QCOM8060:*/hw_version_minor

Date:		Nov 2015

KernelVersion:	4.4

Contact:	"Sinan Kaya <okaya@cudeaurora.org>"

Description:

		Version number minor for the hardware.



What:		/sys/devices/platform/hidma-mgmt*/max_rd_xactions

		/sys/devices/platform/QCOM8060:*/max_rd_xactions

Date:		Nov 2015

KernelVersion:	4.4

Contact:	"Sinan Kaya <okaya@cudeaurora.org>"

Description:

		Contains a value between 0 and 31. Maximum number of

		read transactions that can be issued back to back.

		Choosing a higher number gives better performance but

		can also cause performance reduction to other peripherals

		sharing the same bus.



What:		/sys/devices/platform/hidma-mgmt*/max_read_request

		/sys/devices/platform/QCOM8060:*/max_read_request

Date:		Nov 2015

KernelVersion:	4.4

Contact:	"Sinan Kaya <okaya@cudeaurora.org>"

Description:

		Size of each read request. The value needs to be a power

		of two and can be between 128 and 1024.



What:		/sys/devices/platform/hidma-mgmt*/max_wr_xactions

		/sys/devices/platform/QCOM8060:*/max_wr_xactions

Date:		Nov 2015

KernelVersion:	4.4

Contact:	"Sinan Kaya <okaya@cudeaurora.org>"

Description:

		Contains a value between 0 and 31. Maximum number of

		write transactions that can be issued back to back.

		Choosing a higher number gives better performance but

		can also cause performance reduction to other peripherals

		sharing the same bus.





What:		/sys/devices/platform/hidma-mgmt*/max_write_request

		/sys/devices/platform/QCOM8060:*/max_write_request

Date:		Nov 2015

KernelVersion:	4.4

Contact:	"Sinan Kaya <okaya@cudeaurora.org>"

Description:

		Size of each write request. The value needs to be a power

		of two and can be between 128 and 1024.

drivers/dma/qcom/Kconfig

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@@ -6,3 +6,14 @@ config QCOM_BAM_DMA 
	---help---

	  Enable support for the QCOM BAM DMA controller.  This controller

	  provides DMA capabilities for a variety of on-chip devices.



config QCOM_HIDMA_MGMT

	tristate "Qualcomm Technologies HIDMA Management support"

	select DMA_ENGINE

	help

	  Enable support for the Qualcomm Technologies HIDMA Management.

	  Each DMA device requires one management interface driver

	  for basic initialization before QCOM_HIDMA channel driver can

	  start managing the channels. In a virtualized environment,

	  the guest OS would run QCOM_HIDMA channel driver and the

	  host would run the QCOM_HIDMA_MGMT management driver.

drivers/dma/qcom/Makefile

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Original line number Diff line number Diff line 
obj-$(CONFIG_QCOM_BAM_DMA) += bam_dma.o

obj-$(CONFIG_QCOM_HIDMA_MGMT) += hdma_mgmt.o

hdma_mgmt-objs	 := hidma_mgmt.o hidma_mgmt_sys.o

drivers/dma/qcom/hidma_mgmt.c

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/*

 * Qualcomm Technologies HIDMA DMA engine Management interface

 *

 * Copyright (c) 2015, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#include <linux/dmaengine.h>

#include <linux/acpi.h>

#include <linux/of.h>

#include <linux/property.h>

#include <linux/interrupt.h>

#include <linux/platform_device.h>

#include <linux/module.h>

#include <linux/uaccess.h>

#include <linux/slab.h>

#include <linux/pm_runtime.h>

#include <linux/bitops.h>



#include "hidma_mgmt.h"



#define HIDMA_QOS_N_OFFSET		0x300

#define HIDMA_CFG_OFFSET		0x400

#define HIDMA_MAX_BUS_REQ_LEN_OFFSET	0x41C

#define HIDMA_MAX_XACTIONS_OFFSET	0x420

#define HIDMA_HW_VERSION_OFFSET	0x424

#define HIDMA_CHRESET_TIMEOUT_OFFSET	0x418



#define HIDMA_MAX_WR_XACTIONS_MASK	GENMASK(4, 0)

#define HIDMA_MAX_RD_XACTIONS_MASK	GENMASK(4, 0)

#define HIDMA_WEIGHT_MASK		GENMASK(6, 0)

#define HIDMA_MAX_BUS_REQ_LEN_MASK	GENMASK(15, 0)

#define HIDMA_CHRESET_TIMEOUT_MASK	GENMASK(19, 0)



#define HIDMA_MAX_WR_XACTIONS_BIT_POS	16

#define HIDMA_MAX_BUS_WR_REQ_BIT_POS	16

#define HIDMA_WRR_BIT_POS		8

#define HIDMA_PRIORITY_BIT_POS		15



#define HIDMA_AUTOSUSPEND_TIMEOUT	2000

#define HIDMA_MAX_CHANNEL_WEIGHT	15



int hidma_mgmt_setup(struct hidma_mgmt_dev *mgmtdev)

{

	unsigned int i;

	u32 val;



	if (!is_power_of_2(mgmtdev->max_write_request) ||

	    (mgmtdev->max_write_request < 128) ||

	    (mgmtdev->max_write_request > 1024)) {

		dev_err(&mgmtdev->pdev->dev, "invalid write request %d\n",

			mgmtdev->max_write_request);

		return -EINVAL;

	}



	if (!is_power_of_2(mgmtdev->max_read_request) ||

	    (mgmtdev->max_read_request < 128) ||

	    (mgmtdev->max_read_request > 1024)) {

		dev_err(&mgmtdev->pdev->dev, "invalid read request %d\n",

			mgmtdev->max_read_request);

		return -EINVAL;

	}



	if (mgmtdev->max_wr_xactions > HIDMA_MAX_WR_XACTIONS_MASK) {

		dev_err(&mgmtdev->pdev->dev,

			"max_wr_xactions cannot be bigger than %ld\n",

			HIDMA_MAX_WR_XACTIONS_MASK);

		return -EINVAL;

	}



	if (mgmtdev->max_rd_xactions > HIDMA_MAX_RD_XACTIONS_MASK) {

		dev_err(&mgmtdev->pdev->dev,

			"max_rd_xactions cannot be bigger than %ld\n",

			HIDMA_MAX_RD_XACTIONS_MASK);

		return -EINVAL;

	}



	for (i = 0; i < mgmtdev->dma_channels; i++) {

		if (mgmtdev->priority[i] > 1) {

			dev_err(&mgmtdev->pdev->dev,

				"priority can be 0 or 1\n");

			return -EINVAL;

		}



		if (mgmtdev->weight[i] > HIDMA_MAX_CHANNEL_WEIGHT) {

			dev_err(&mgmtdev->pdev->dev,

				"max value of weight can be %d.\n",

				HIDMA_MAX_CHANNEL_WEIGHT);

			return -EINVAL;

		}



		/* weight needs to be at least one */

		if (mgmtdev->weight[i] == 0)

			mgmtdev->weight[i] = 1;

	}



	pm_runtime_get_sync(&mgmtdev->pdev->dev);

	val = readl(mgmtdev->virtaddr + HIDMA_MAX_BUS_REQ_LEN_OFFSET);

	val &= ~(HIDMA_MAX_BUS_REQ_LEN_MASK << HIDMA_MAX_BUS_WR_REQ_BIT_POS);

	val |= mgmtdev->max_write_request << HIDMA_MAX_BUS_WR_REQ_BIT_POS;

	val &= ~HIDMA_MAX_BUS_REQ_LEN_MASK;

	val |= mgmtdev->max_read_request;

	writel(val, mgmtdev->virtaddr + HIDMA_MAX_BUS_REQ_LEN_OFFSET);



	val = readl(mgmtdev->virtaddr + HIDMA_MAX_XACTIONS_OFFSET);

	val &= ~(HIDMA_MAX_WR_XACTIONS_MASK << HIDMA_MAX_WR_XACTIONS_BIT_POS);

	val |= mgmtdev->max_wr_xactions << HIDMA_MAX_WR_XACTIONS_BIT_POS;

	val &= ~HIDMA_MAX_RD_XACTIONS_MASK;

	val |= mgmtdev->max_rd_xactions;

	writel(val, mgmtdev->virtaddr + HIDMA_MAX_XACTIONS_OFFSET);



	mgmtdev->hw_version =

	    readl(mgmtdev->virtaddr + HIDMA_HW_VERSION_OFFSET);

	mgmtdev->hw_version_major = (mgmtdev->hw_version >> 28) & 0xF;

	mgmtdev->hw_version_minor = (mgmtdev->hw_version >> 16) & 0xF;



	for (i = 0; i < mgmtdev->dma_channels; i++) {

		u32 weight = mgmtdev->weight[i];

		u32 priority = mgmtdev->priority[i];



		val = readl(mgmtdev->virtaddr + HIDMA_QOS_N_OFFSET + (4 * i));

		val &= ~(1 << HIDMA_PRIORITY_BIT_POS);

		val |= (priority & 0x1) << HIDMA_PRIORITY_BIT_POS;

		val &= ~(HIDMA_WEIGHT_MASK << HIDMA_WRR_BIT_POS);

		val |= (weight & HIDMA_WEIGHT_MASK) << HIDMA_WRR_BIT_POS;

		writel(val, mgmtdev->virtaddr + HIDMA_QOS_N_OFFSET + (4 * i));

	}



	val = readl(mgmtdev->virtaddr + HIDMA_CHRESET_TIMEOUT_OFFSET);

	val &= ~HIDMA_CHRESET_TIMEOUT_MASK;

	val |= mgmtdev->chreset_timeout_cycles & HIDMA_CHRESET_TIMEOUT_MASK;

	writel(val, mgmtdev->virtaddr + HIDMA_CHRESET_TIMEOUT_OFFSET);



	pm_runtime_mark_last_busy(&mgmtdev->pdev->dev);

	pm_runtime_put_autosuspend(&mgmtdev->pdev->dev);

	return 0;

}

EXPORT_SYMBOL_GPL(hidma_mgmt_setup);



static int hidma_mgmt_probe(struct platform_device *pdev)

{

	struct hidma_mgmt_dev *mgmtdev;

	struct resource *res;

	void __iomem *virtaddr;

	int irq;

	int rc;

	u32 val;



	pm_runtime_set_autosuspend_delay(&pdev->dev, HIDMA_AUTOSUSPEND_TIMEOUT);

	pm_runtime_use_autosuspend(&pdev->dev);

	pm_runtime_set_active(&pdev->dev);

	pm_runtime_enable(&pdev->dev);

	pm_runtime_get_sync(&pdev->dev);



	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	virtaddr = devm_ioremap_resource(&pdev->dev, res);

	if (IS_ERR(virtaddr)) {

		rc = -ENOMEM;

		goto out;

	}



	irq = platform_get_irq(pdev, 0);

	if (irq < 0) {

		dev_err(&pdev->dev, "irq resources not found\n");

		rc = irq;

		goto out;

	}



	mgmtdev = devm_kzalloc(&pdev->dev, sizeof(*mgmtdev), GFP_KERNEL);

	if (!mgmtdev) {

		rc = -ENOMEM;

		goto out;

	}



	mgmtdev->pdev = pdev;

	mgmtdev->addrsize = resource_size(res);

	mgmtdev->virtaddr = virtaddr;



	rc = device_property_read_u32(&pdev->dev, "dma-channels",

				      &mgmtdev->dma_channels);

	if (rc) {

		dev_err(&pdev->dev, "number of channels missing\n");

		goto out;

	}



	rc = device_property_read_u32(&pdev->dev,

				      "channel-reset-timeout-cycles",

				      &mgmtdev->chreset_timeout_cycles);

	if (rc) {

		dev_err(&pdev->dev, "channel reset timeout missing\n");

		goto out;

	}



	rc = device_property_read_u32(&pdev->dev, "max-write-burst-bytes",

				      &mgmtdev->max_write_request);

	if (rc) {

		dev_err(&pdev->dev, "max-write-burst-bytes missing\n");

		goto out;

	}



	rc = device_property_read_u32(&pdev->dev, "max-read-burst-bytes",

				      &mgmtdev->max_read_request);

	if (rc) {

		dev_err(&pdev->dev, "max-read-burst-bytes missing\n");

		goto out;

	}



	rc = device_property_read_u32(&pdev->dev, "max-write-transactions",

				      &mgmtdev->max_wr_xactions);

	if (rc) {

		dev_err(&pdev->dev, "max-write-transactions missing\n");

		goto out;

	}



	rc = device_property_read_u32(&pdev->dev, "max-read-transactions",

				      &mgmtdev->max_rd_xactions);

	if (rc) {

		dev_err(&pdev->dev, "max-read-transactions missing\n");

		goto out;

	}



	mgmtdev->priority = devm_kcalloc(&pdev->dev,

					 mgmtdev->dma_channels,

					 sizeof(*mgmtdev->priority),

					 GFP_KERNEL);

	if (!mgmtdev->priority) {

		rc = -ENOMEM;

		goto out;

	}



	mgmtdev->weight = devm_kcalloc(&pdev->dev,

				       mgmtdev->dma_channels,

				       sizeof(*mgmtdev->weight), GFP_KERNEL);

	if (!mgmtdev->weight) {

		rc = -ENOMEM;

		goto out;

	}



	rc = hidma_mgmt_setup(mgmtdev);

	if (rc) {

		dev_err(&pdev->dev, "setup failed\n");

		goto out;

	}



	/* start the HW */

	val = readl(mgmtdev->virtaddr + HIDMA_CFG_OFFSET);

	val |= 1;

	writel(val, mgmtdev->virtaddr + HIDMA_CFG_OFFSET);



	rc = hidma_mgmt_init_sys(mgmtdev);

	if (rc) {

		dev_err(&pdev->dev, "sysfs setup failed\n");

		goto out;

	}



	dev_info(&pdev->dev,

		 "HW rev: %d.%d @ %pa with %d physical channels\n",

		 mgmtdev->hw_version_major, mgmtdev->hw_version_minor,

		 &res->start, mgmtdev->dma_channels);



	platform_set_drvdata(pdev, mgmtdev);

	pm_runtime_mark_last_busy(&pdev->dev);

	pm_runtime_put_autosuspend(&pdev->dev);

	return 0;

out:

	pm_runtime_put_sync_suspend(&pdev->dev);

	pm_runtime_disable(&pdev->dev);

	return rc;

}



#if IS_ENABLED(CONFIG_ACPI)

static const struct acpi_device_id hidma_mgmt_acpi_ids[] = {

	{"QCOM8060"},

	{},

};

#endif



static const struct of_device_id hidma_mgmt_match[] = {

	{.compatible = "qcom,hidma-mgmt-1.0",},

	{},

};

MODULE_DEVICE_TABLE(of, hidma_mgmt_match);



static struct platform_driver hidma_mgmt_driver = {

	.probe = hidma_mgmt_probe,

	.driver = {

		   .name = "hidma-mgmt",

		   .of_match_table = hidma_mgmt_match,

		   .acpi_match_table = ACPI_PTR(hidma_mgmt_acpi_ids),

	},

};



module_platform_driver(hidma_mgmt_driver);

MODULE_LICENSE("GPL v2");

drivers/dma/qcom/hidma_mgmt.h

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/*

 * Qualcomm Technologies HIDMA Management common header

 *

 * Copyright (c) 2015, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



struct hidma_mgmt_dev {

	u8 hw_version_major;

	u8 hw_version_minor;



	u32 max_wr_xactions;

	u32 max_rd_xactions;

	u32 max_write_request;

	u32 max_read_request;

	u32 dma_channels;

	u32 chreset_timeout_cycles;

	u32 hw_version;

	u32 *priority;

	u32 *weight;



	/* Hardware device constants */

	void __iomem *virtaddr;

	resource_size_t addrsize;



	struct kobject **chroots;

	struct platform_device *pdev;

};



int hidma_mgmt_init_sys(struct hidma_mgmt_dev *dev);

int hidma_mgmt_setup(struct hidma_mgmt_dev *mgmtdev);

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