Commit 7f884b64 authored by Maxime Ripard's avatar Maxime Ripard Committed by Linus Walleij
Browse files

pinctrl: sunxi: Add external interrupt functions 



The A10 and A13 has a few pins that can be muxed into a particular
function that can be used as an interrupt source. Add the available
pins for such functions to the A10 and A13 description array.

Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 60242db1

drivers/pinctrl/pinctrl-sunxi.c

+73 −26
Original line number Diff line number Diff line
@@ -675,6 +675,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { 
		SUNXI_FUNCTION(0x2, "lcd1"),		/* D0 */

		SUNXI_FUNCTION(0x3, "pata"),		/* ATAA0 */

		SUNXI_FUNCTION(0x4, "uart3"),		/* TX */

		SUNXI_FUNCTION_IRQ(0x6, 0),		/* EINT0 */

		SUNXI_FUNCTION(0x7, "csi1")),		/* D0 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1,

		SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -682,6 +683,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { 
		SUNXI_FUNCTION(0x2, "lcd1"),		/* D1 */

		SUNXI_FUNCTION(0x3, "pata"),		/* ATAA1 */

		SUNXI_FUNCTION(0x4, "uart3"),		/* RX */

		SUNXI_FUNCTION_IRQ(0x6, 1),		/* EINT1 */

		SUNXI_FUNCTION(0x7, "csi1")),		/* D1 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2,

		SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -689,6 +691,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { 
		SUNXI_FUNCTION(0x2, "lcd1"),		/* D2 */

		SUNXI_FUNCTION(0x3, "pata"),		/* ATAA2 */

		SUNXI_FUNCTION(0x4, "uart3"),		/* RTS */

		SUNXI_FUNCTION_IRQ(0x6, 2),		/* EINT2 */

		SUNXI_FUNCTION(0x7, "csi1")),		/* D2 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3,

		SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -696,6 +699,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { 
		SUNXI_FUNCTION(0x2, "lcd1"),		/* D3 */

		SUNXI_FUNCTION(0x3, "pata"),		/* ATAIRQ */

		SUNXI_FUNCTION(0x4, "uart3"),		/* CTS */

		SUNXI_FUNCTION_IRQ(0x6, 3),		/* EINT3 */

		SUNXI_FUNCTION(0x7, "csi1")),		/* D3 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4,

		SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -703,6 +707,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { 
		SUNXI_FUNCTION(0x2, "lcd1"),		/* D4 */

		SUNXI_FUNCTION(0x3, "pata"),		/* ATAD0 */

		SUNXI_FUNCTION(0x4, "uart4"),		/* TX */

		SUNXI_FUNCTION_IRQ(0x6, 4),		/* EINT4 */

		SUNXI_FUNCTION(0x7, "csi1")),		/* D4 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5,

		SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -710,6 +715,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { 
		SUNXI_FUNCTION(0x2, "lcd1"),		/* D5 */

		SUNXI_FUNCTION(0x3, "pata"),		/* ATAD1 */

		SUNXI_FUNCTION(0x4, "uart4"),		/* RX */

		SUNXI_FUNCTION_IRQ(0x6, 5),		/* EINT5 */

		SUNXI_FUNCTION(0x7, "csi1")),		/* D5 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6,

		SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -718,6 +724,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { 
		SUNXI_FUNCTION(0x3, "pata"),		/* ATAD2 */

		SUNXI_FUNCTION(0x4, "uart5"),		/* TX */

		SUNXI_FUNCTION(0x5, "ms"),		/* BS */

		SUNXI_FUNCTION_IRQ(0x6, 6),		/* EINT6 */

		SUNXI_FUNCTION(0x7, "csi1")),		/* D6 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7,

		SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -726,6 +733,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { 
		SUNXI_FUNCTION(0x3, "pata"),		/* ATAD3 */

		SUNXI_FUNCTION(0x4, "uart5"),		/* RX */

		SUNXI_FUNCTION(0x5, "ms"),		/* CLK */

		SUNXI_FUNCTION_IRQ(0x6, 7),		/* EINT7 */

		SUNXI_FUNCTION(0x7, "csi1")),		/* D7 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8,

		SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -734,6 +742,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { 
		SUNXI_FUNCTION(0x3, "pata"),		/* ATAD4 */

		SUNXI_FUNCTION(0x4, "keypad"),		/* IN0 */

		SUNXI_FUNCTION(0x5, "ms"),		/* D0 */

		SUNXI_FUNCTION_IRQ(0x6, 8),		/* EINT8 */

		SUNXI_FUNCTION(0x7, "csi1")),		/* D8 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9,

		SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -742,6 +751,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { 
		SUNXI_FUNCTION(0x3, "pata"),		/* ATAD5 */

		SUNXI_FUNCTION(0x4, "keypad"),		/* IN1 */

		SUNXI_FUNCTION(0x5, "ms"),		/* D1 */

		SUNXI_FUNCTION_IRQ(0x6, 9),		/* EINT9 */

		SUNXI_FUNCTION(0x7, "csi1")),		/* D9 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10,

		SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -750,6 +760,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { 
		SUNXI_FUNCTION(0x3, "pata"),		/* ATAD6 */

		SUNXI_FUNCTION(0x4, "keypad"),		/* IN2 */

		SUNXI_FUNCTION(0x5, "ms"),		/* D2 */

		SUNXI_FUNCTION_IRQ(0x6, 10),		/* EINT10 */

		SUNXI_FUNCTION(0x7, "csi1")),		/* D10 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11,

		SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -758,6 +769,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { 
		SUNXI_FUNCTION(0x3, "pata"),		/* ATAD7 */

		SUNXI_FUNCTION(0x4, "keypad"),		/* IN3 */

		SUNXI_FUNCTION(0x5, "ms"),		/* D3 */

		SUNXI_FUNCTION_IRQ(0x6, 11),		/* EINT11 */

		SUNXI_FUNCTION(0x7, "csi1")),		/* D11 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12,

		SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -765,6 +777,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { 
		SUNXI_FUNCTION(0x2, "lcd1"),		/* D12 */

		SUNXI_FUNCTION(0x3, "pata"),		/* ATAD8 */

		SUNXI_FUNCTION(0x4, "ps2"),		/* SCK1 */

		SUNXI_FUNCTION_IRQ(0x6, 12),		/* EINT12 */

		SUNXI_FUNCTION(0x7, "csi1")),		/* D12 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13,

		SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -773,6 +786,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { 
		SUNXI_FUNCTION(0x3, "pata"),		/* ATAD9 */

		SUNXI_FUNCTION(0x4, "ps2"),		/* SDA1 */

		SUNXI_FUNCTION(0x5, "sim"),		/* RST */

		SUNXI_FUNCTION_IRQ(0x6, 13),		/* EINT13 */

		SUNXI_FUNCTION(0x7, "csi1")),		/* D13 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14,

		SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -781,6 +795,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { 
		SUNXI_FUNCTION(0x3, "pata"),		/* ATAD10 */

		SUNXI_FUNCTION(0x4, "keypad"),		/* IN4 */

		SUNXI_FUNCTION(0x5, "sim"),		/* VPPEN */

		SUNXI_FUNCTION_IRQ(0x6, 14),		/* EINT14 */

		SUNXI_FUNCTION(0x7, "csi1")),		/* D14 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15,

		SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -789,6 +804,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { 
		SUNXI_FUNCTION(0x3, "pata"),		/* ATAD11 */

		SUNXI_FUNCTION(0x4, "keypad"),		/* IN5 */

		SUNXI_FUNCTION(0x5, "sim"),		/* VPPPP */

		SUNXI_FUNCTION_IRQ(0x6, 15),		/* EINT15 */

		SUNXI_FUNCTION(0x7, "csi1")),		/* D15 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16,

		SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -796,6 +812,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { 
		SUNXI_FUNCTION(0x2, "lcd1"),		/* D16 */

		SUNXI_FUNCTION(0x3, "pata"),		/* ATAD12 */

		SUNXI_FUNCTION(0x4, "keypad"),		/* IN6 */

		SUNXI_FUNCTION_IRQ(0x6, 16),		/* EINT16 */

		SUNXI_FUNCTION(0x7, "csi1")),		/* D16 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17,

		SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -804,6 +821,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { 
		SUNXI_FUNCTION(0x3, "pata"),		/* ATAD13 */

		SUNXI_FUNCTION(0x4, "keypad"),		/* IN7 */

		SUNXI_FUNCTION(0x5, "sim"),		/* VCCEN */

		SUNXI_FUNCTION_IRQ(0x6, 17),		/* EINT17 */

		SUNXI_FUNCTION(0x7, "csi1")),		/* D17 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18,

		SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -812,6 +830,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { 
		SUNXI_FUNCTION(0x3, "pata"),		/* ATAD14 */

		SUNXI_FUNCTION(0x4, "keypad"),		/* OUT0 */

		SUNXI_FUNCTION(0x5, "sim"),		/* SCK */

		SUNXI_FUNCTION_IRQ(0x6, 18),		/* EINT18 */

		SUNXI_FUNCTION(0x7, "csi1")),		/* D18 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19,

		SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -820,6 +839,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { 
		SUNXI_FUNCTION(0x3, "pata"),		/* ATAD15 */

		SUNXI_FUNCTION(0x4, "keypad"),		/* OUT1 */

		SUNXI_FUNCTION(0x5, "sim"),		/* SDA */

		SUNXI_FUNCTION_IRQ(0x6, 19),		/* EINT19 */

		SUNXI_FUNCTION(0x7, "csi1")),		/* D19 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20,

		SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -827,6 +847,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { 
		SUNXI_FUNCTION(0x2, "lcd1"),		/* D20 */

		SUNXI_FUNCTION(0x3, "pata"),		/* ATAOE */

		SUNXI_FUNCTION(0x4, "can"),		/* TX */

		SUNXI_FUNCTION_IRQ(0x6, 20),		/* EINT20 */

		SUNXI_FUNCTION(0x7, "csi1")),		/* D20 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21,

		SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -834,6 +855,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { 
		SUNXI_FUNCTION(0x2, "lcd1"),		/* D21 */

		SUNXI_FUNCTION(0x3, "pata"),		/* ATADREQ */

		SUNXI_FUNCTION(0x4, "can"),		/* RX */

		SUNXI_FUNCTION_IRQ(0x6, 21),		/* EINT21 */

		SUNXI_FUNCTION(0x7, "csi1")),		/* D21 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22,

		SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -925,54 +947,64 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { 
		SUNXI_FUNCTION(0x0, "gpio_in"),

		SUNXI_FUNCTION(0x1, "gpio_out"),

		SUNXI_FUNCTION(0x2, "spi0"),		/* CS0 */

		SUNXI_FUNCTION(0x3, "uart5")),		/* TX */

		SUNXI_FUNCTION(0x3, "uart5"),		/* TX */

		SUNXI_FUNCTION_IRQ(0x6, 22)),		/* EINT22 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PI11,

		SUNXI_FUNCTION(0x0, "gpio_in"),

		SUNXI_FUNCTION(0x1, "gpio_out"),

		SUNXI_FUNCTION(0x2, "spi0"),		/* CLK */

		SUNXI_FUNCTION(0x3, "uart5")),		/* RX */

		SUNXI_FUNCTION(0x3, "uart5"),		/* RX */

		SUNXI_FUNCTION_IRQ(0x6, 23)),		/* EINT23 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PI12,

		SUNXI_FUNCTION(0x0, "gpio_in"),

		SUNXI_FUNCTION(0x1, "gpio_out"),

		SUNXI_FUNCTION(0x2, "spi0"),		/* MOSI */

		SUNXI_FUNCTION(0x3, "uart6")),		/* TX */

		SUNXI_FUNCTION(0x3, "uart6"),		/* TX */

		SUNXI_FUNCTION_IRQ(0x6, 24)),		/* EINT24 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13,

		SUNXI_FUNCTION(0x0, "gpio_in"),

		SUNXI_FUNCTION(0x1, "gpio_out"),

		SUNXI_FUNCTION(0x2, "spi0"),		/* MISO */

		SUNXI_FUNCTION(0x3, "uart6")),		/* RX */

		SUNXI_FUNCTION(0x3, "uart6"),		/* RX */

		SUNXI_FUNCTION_IRQ(0x6, 25)),		/* EINT25 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14,

		SUNXI_FUNCTION(0x0, "gpio_in"),

		SUNXI_FUNCTION(0x1, "gpio_out"),

		SUNXI_FUNCTION(0x2, "spi0"),		/* CS1 */

		SUNXI_FUNCTION(0x3, "ps2"),		/* SCK1 */

		SUNXI_FUNCTION(0x4, "timer4")),		/* TCLKIN0 */

		SUNXI_FUNCTION(0x4, "timer4"),		/* TCLKIN0 */

		SUNXI_FUNCTION_IRQ(0x6, 26)),		/* EINT26 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PI15,

		SUNXI_FUNCTION(0x0, "gpio_in"),

		SUNXI_FUNCTION(0x1, "gpio_out"),

		SUNXI_FUNCTION(0x2, "spi1"),		/* CS1 */

		SUNXI_FUNCTION(0x3, "ps2"),		/* SDA1 */

		SUNXI_FUNCTION(0x4, "timer5")),		/* TCLKIN1 */

		SUNXI_FUNCTION(0x4, "timer5"),		/* TCLKIN1 */

		SUNXI_FUNCTION_IRQ(0x6, 27)),		/* EINT27 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PI16,

		SUNXI_FUNCTION(0x0, "gpio_in"),

		SUNXI_FUNCTION(0x1, "gpio_out"),

		SUNXI_FUNCTION(0x2, "spi1"),		/* CS0 */

		SUNXI_FUNCTION(0x3, "uart2")),		/* RTS */

		SUNXI_FUNCTION(0x3, "uart2"),		/* RTS */

		SUNXI_FUNCTION_IRQ(0x6, 28)),		/* EINT28 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PI17,

		SUNXI_FUNCTION(0x0, "gpio_in"),

		SUNXI_FUNCTION(0x1, "gpio_out"),

		SUNXI_FUNCTION(0x2, "spi1"),		/* CLK */

		SUNXI_FUNCTION(0x3, "uart2")),		/* CTS */

		SUNXI_FUNCTION(0x3, "uart2"),		/* CTS */

		SUNXI_FUNCTION_IRQ(0x6, 29)),		/* EINT29 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PI18,

		SUNXI_FUNCTION(0x0, "gpio_in"),

		SUNXI_FUNCTION(0x1, "gpio_out"),

		SUNXI_FUNCTION(0x2, "spi1"),		/* MOSI */

		SUNXI_FUNCTION(0x3, "uart2")),		/* TX */

		SUNXI_FUNCTION(0x3, "uart2"),		/* TX */

		SUNXI_FUNCTION_IRQ(0x6, 30)),		/* EINT30 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PI19,

		SUNXI_FUNCTION(0x0, "gpio_in"),

		SUNXI_FUNCTION(0x1, "gpio_out"),

		SUNXI_FUNCTION(0x2, "spi1"),		/* MISO */

		SUNXI_FUNCTION(0x3, "uart2")),		/* RX */

		SUNXI_FUNCTION(0x3, "uart2"),		/* RX */

		SUNXI_FUNCTION_IRQ(0x6, 31)),		/* EINT31 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PI20,

		SUNXI_FUNCTION(0x0, "gpio_in"),

		SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -1000,20 +1032,24 @@ static const struct sunxi_desc_pin sun5i_a13_pins[] = { 
	SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,

		SUNXI_FUNCTION(0x0, "gpio_in"),

		SUNXI_FUNCTION(0x1, "gpio_out"),

		SUNXI_FUNCTION(0x2, "pwm")),

		SUNXI_FUNCTION(0x2, "pwm"),

		SUNXI_FUNCTION_IRQ(0x6, 16)),		/* EINT16 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,

		SUNXI_FUNCTION(0x0, "gpio_in"),

		SUNXI_FUNCTION(0x1, "gpio_out"),

		SUNXI_FUNCTION(0x2, "ir0")),		/* TX */

		SUNXI_FUNCTION(0x2, "ir0"),		/* TX */

		SUNXI_FUNCTION_IRQ(0x6, 17)),		/* EINT17 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,

		SUNXI_FUNCTION(0x0, "gpio_in"),

		SUNXI_FUNCTION(0x1, "gpio_out"),

		SUNXI_FUNCTION(0x2, "ir0")),		/* RX */

		SUNXI_FUNCTION(0x2, "ir0"),		/* RX */

		SUNXI_FUNCTION_IRQ(0x6, 18)),		/* EINT18 */

	/* Hole */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,

		SUNXI_FUNCTION(0x0, "gpio_in"),

		SUNXI_FUNCTION(0x1, "gpio_out"),

		SUNXI_FUNCTION(0x2, "spi2")),		/* CS1 */

		SUNXI_FUNCTION(0x2, "spi2"),		/* CS1 */

		SUNXI_FUNCTION_IRQ(0x6, 24)),		/* EINT24 */

	/* Hole */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,

		SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -1211,11 +1247,13 @@ static const struct sunxi_desc_pin sun5i_a13_pins[] = { 
	SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,

		SUNXI_FUNCTION(0x0, "gpio_in"),

		SUNXI_FUNCTION(0x3, "csi0"),		/* PCLK */

		SUNXI_FUNCTION(0x4, "spi2")),		/* CS0 */

		SUNXI_FUNCTION(0x4, "spi2"),		/* CS0 */

		SUNXI_FUNCTION_IRQ(0x6, 14)),		/* EINT14 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,

		SUNXI_FUNCTION(0x0, "gpio_in"),

		SUNXI_FUNCTION(0x3, "csi0"),		/* MCLK */

		SUNXI_FUNCTION(0x4, "spi2")),		/* CLK */

		SUNXI_FUNCTION(0x4, "spi2"),		/* CLK */

		SUNXI_FUNCTION_IRQ(0x6, 15)),		/* EINT15 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,

		SUNXI_FUNCTION(0x0, "gpio_in"),

		SUNXI_FUNCTION(0x3, "csi0"),		/* HSYNC */
@@ -1293,44 +1331,53 @@ static const struct sunxi_desc_pin sun5i_a13_pins[] = { 
	/* Hole */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,

		SUNXI_FUNCTION(0x0, "gpio_in"),

		SUNXI_FUNCTION(0x1, "gpio_out")),

		SUNXI_FUNCTION(0x1, "gpio_out"),

		SUNXI_FUNCTION_IRQ(0x6, 0)),		/* EINT0 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,

		SUNXI_FUNCTION(0x0, "gpio_in"),

		SUNXI_FUNCTION(0x1, "gpio_out")),

		SUNXI_FUNCTION(0x1, "gpio_out"),

		SUNXI_FUNCTION_IRQ(0x6, 1)),		/* EINT1 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,

		SUNXI_FUNCTION(0x0, "gpio_in"),

		SUNXI_FUNCTION(0x1, "gpio_out")),

		SUNXI_FUNCTION(0x1, "gpio_out"),

		SUNXI_FUNCTION_IRQ(0x6, 2)),		/* EINT2 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,

		SUNXI_FUNCTION(0x0, "gpio_in"),

		SUNXI_FUNCTION(0x1, "gpio_out"),

		SUNXI_FUNCTION(0x2, "mmc1"),		/* CMD */

		SUNXI_FUNCTION(0x4, "uart1")),		/* TX */

		SUNXI_FUNCTION(0x4, "uart1"),		/* TX */

		SUNXI_FUNCTION_IRQ(0x6, 3)),		/* EINT3 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,

		SUNXI_FUNCTION(0x0, "gpio_in"),

		SUNXI_FUNCTION(0x1, "gpio_out"),

		SUNXI_FUNCTION(0x2, "mmc1"),		/* CLK */

		SUNXI_FUNCTION(0x4, "uart1")),		/* RX */

		SUNXI_FUNCTION(0x4, "uart1"),		/* RX */

		SUNXI_FUNCTION_IRQ(0x6, 4)),		/* EINT4 */

	/* Hole */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,

		SUNXI_FUNCTION(0x0, "gpio_in"),

		SUNXI_FUNCTION(0x1, "gpio_out"),

		SUNXI_FUNCTION(0x2, "spi1"),		/* CS0 */

		SUNXI_FUNCTION(0x3, "uart3")),		/* TX */

		SUNXI_FUNCTION(0x3, "uart3"),		/* TX */

		SUNXI_FUNCTION_IRQ(0x6, 9)),		/* EINT9 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,

		SUNXI_FUNCTION(0x0, "gpio_in"),

		SUNXI_FUNCTION(0x1, "gpio_out"),

		SUNXI_FUNCTION(0x2, "spi1"),		/* CLK */

		SUNXI_FUNCTION(0x3, "uart3")),		/* RX */

		SUNXI_FUNCTION(0x3, "uart3"),		/* RX */

		SUNXI_FUNCTION_IRQ(0x6, 10)),		/* EINT10 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,

		SUNXI_FUNCTION(0x0, "gpio_in"),

		SUNXI_FUNCTION(0x1, "gpio_out"),

		SUNXI_FUNCTION(0x2, "spi1"),		/* MOSI */

		SUNXI_FUNCTION(0x3, "uart3")),		/* CTS */

		SUNXI_FUNCTION(0x3, "uart3"),		/* CTS */

		SUNXI_FUNCTION_IRQ(0x6, 11)),		/* EINT11 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12,

		SUNXI_FUNCTION(0x0, "gpio_in"),

		SUNXI_FUNCTION(0x1, "gpio_out"),

		SUNXI_FUNCTION(0x2, "spi1"),		/* MISO */

		SUNXI_FUNCTION(0x3, "uart3")),		/* RTS */

		SUNXI_FUNCTION(0x3, "uart3"),		/* RTS */

		SUNXI_FUNCTION_IRQ(0x6, 12)),		/* EINT12 */

};



static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = {

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