Commit 7f2c2f38 authored by Wolfram Sang's avatar Wolfram Sang Committed by Geert Uytterhoeven
Browse files

clk: renesas: rcar-gen3: Remove stp_ck handling for SDHI 



There is no case (and none foreseen) where we would need to disable the
SDn clock. So, for simplicity, remove its handling.

Signed-off-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20200922120036.10298-1-wsa+renesas@sang-engineering.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 3650b228

drivers/clk/renesas/rcar-gen3-cpg.c

+25 −26
Original line number Diff line number Diff line
@@ -224,10 +224,9 @@ static struct clk * __init cpg_z_clk_register(const char *name, 
#define CPG_SD_STP_MASK		(CPG_SD_STP_HCK | CPG_SD_STP_CK)

#define CPG_SD_FC_MASK		(0x7 << 2 | 0x3 << 0)



#define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \

#define CPG_SD_DIV_TABLE_DATA(stp_hck, sd_srcfc, sd_fc, sd_div) \

{ \

	.val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \

	       ((stp_ck) ? CPG_SD_STP_CK : 0) | \

	       ((sd_srcfc) << 2) | \

	       ((sd_fc) << 0), \

	.div = (sd_div), \
@@ -248,35 +247,35 @@ struct sd_clock { 


/* SDn divider

 *           sd_srcfc   sd_fc   div

 * stp_hck   stp_ck    (div)      (div)     = sd_srcfc x sd_fc

 *-------------------------------------------------------------------

 *  0         0         0 (1)      1 (4)      4 : SDR104 / HS200 / HS400 (8 TAP)

 *  0         0         1 (2)      1 (4)      8 : SDR50

 *  1         0         2 (4)      1 (4)     16 : HS / SDR25

 *  1         0         3 (8)      1 (4)     32 : NS / SDR12

 *  1         0         4 (16)     1 (4)     64

 *  0         0         0 (1)      0 (2)      2

 *  0         0         1 (2)      0 (2)      4 : SDR104 / HS200 / HS400 (4 TAP)

 *  1         0         2 (4)      0 (2)      8

 *  1         0         3 (8)      0 (2)     16

 *  1         0         4 (16)     0 (2)     32

 * stp_hck   (div)      (div)     = sd_srcfc x sd_fc

 *---------------------------------------------------------

 *  0         0 (1)      1 (4)      4 : SDR104 / HS200 / HS400 (8 TAP)

 *  0         1 (2)      1 (4)      8 : SDR50

 *  1         2 (4)      1 (4)     16 : HS / SDR25

 *  1         3 (8)      1 (4)     32 : NS / SDR12

 *  1         4 (16)     1 (4)     64

 *  0         0 (1)      0 (2)      2

 *  0         1 (2)      0 (2)      4 : SDR104 / HS200 / HS400 (4 TAP)

 *  1         2 (4)      0 (2)      8

 *  1         3 (8)      0 (2)     16

 *  1         4 (16)     0 (2)     32

 *

 *  NOTE: There is a quirk option to ignore the first row of the dividers

 *  table when searching for suitable settings. This is because HS400 on

 *  early ES versions of H3 and M3-W requires a specific setting to work.

 */

static const struct sd_div_table cpg_sd_div_table[] = {

/*	CPG_SD_DIV_TABLE_DATA(stp_hck,  stp_ck,   sd_srcfc,   sd_fc,  sd_div) */

	CPG_SD_DIV_TABLE_DATA(0,        0,        0,          1,        4),

	CPG_SD_DIV_TABLE_DATA(0,        0,        1,          1,        8),

	CPG_SD_DIV_TABLE_DATA(1,        0,        2,          1,       16),

	CPG_SD_DIV_TABLE_DATA(1,        0,        3,          1,       32),

	CPG_SD_DIV_TABLE_DATA(1,        0,        4,          1,       64),

	CPG_SD_DIV_TABLE_DATA(0,        0,        0,          0,        2),

	CPG_SD_DIV_TABLE_DATA(0,        0,        1,          0,        4),

	CPG_SD_DIV_TABLE_DATA(1,        0,        2,          0,        8),

	CPG_SD_DIV_TABLE_DATA(1,        0,        3,          0,       16),

	CPG_SD_DIV_TABLE_DATA(1,        0,        4,          0,       32),

/*	CPG_SD_DIV_TABLE_DATA(stp_hck,  sd_srcfc,   sd_fc,  sd_div) */

	CPG_SD_DIV_TABLE_DATA(0,        0,          1,        4),

	CPG_SD_DIV_TABLE_DATA(0,        1,          1,        8),

	CPG_SD_DIV_TABLE_DATA(1,        2,          1,       16),

	CPG_SD_DIV_TABLE_DATA(1,        3,          1,       32),

	CPG_SD_DIV_TABLE_DATA(1,        4,          1,       64),

	CPG_SD_DIV_TABLE_DATA(0,        0,          0,        2),

	CPG_SD_DIV_TABLE_DATA(0,        1,          0,        4),

	CPG_SD_DIV_TABLE_DATA(1,        2,          0,        8),

	CPG_SD_DIV_TABLE_DATA(1,        3,          0,       16),

	CPG_SD_DIV_TABLE_DATA(1,        4,          0,       32),

};



#define to_sd_clock(_hw) container_of(_hw, struct sd_clock, hw)

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