Commit 7ef8aa72 authored by Andre Przywara's avatar Andre Przywara Committed by H. Peter Anvin
Browse files

x86, cpu: Fix renamed, not-yet-shipping AMD CPUID feature bit 



The AMD SSE5 feature set as-it has been replaced by some extensions
to the AVX instruction set. Thus the bit formerly advertised as SSE5
is re-used for one of these extensions (XOP).
Although this changes the /proc/cpuinfo output, it is not user visible, as
there are no CPUs (yet) having this feature.
To avoid confusion this should be added to the stable series, too.

Cc: stable@kernel.org [.32.x .34.x, .35.x]
Signed-off-by: default avatarAndre Przywara <andre.przywara@amd.com>
LKML-Reference: <1283778860-26843-2-git-send-email-andre.przywara@amd.com>
Signed-off-by: default avatarH. Peter Anvin <hpa@linux.intel.com>
parent d9fadd7b

arch/x86/include/asm/cpufeature.h

+1 −1
Original line number Diff line number Diff line
@@ -152,7 +152,7 @@ 
#define X86_FEATURE_3DNOWPREFETCH (6*32+ 8) /* 3DNow prefetch instructions */

#define X86_FEATURE_OSVW	(6*32+ 9) /* OS Visible Workaround */

#define X86_FEATURE_IBS		(6*32+10) /* Instruction Based Sampling */

#define X86_FEATURE_SSE5	(6*32+11) /* SSE-5 */

#define X86_FEATURE_XOP		(6*32+11) /* extended AVX instructions */

#define X86_FEATURE_SKINIT	(6*32+12) /* SKINIT/STGI instructions */

#define X86_FEATURE_WDT		(6*32+13) /* Watchdog timer */

#define X86_FEATURE_NODEID_MSR	(6*32+19) /* NodeId MSR */

arch/x86/kvm/x86.c

+1 −1
Original line number Diff line number Diff line
@@ -1996,7 +1996,7 @@ static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, 
	const u32 kvm_supported_word6_x86_features =

		F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |

		F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |

		F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |

		F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(XOP) |

		0 /* SKINIT */ | 0 /* WDT */;



	/* all calls to cpuid_count() should be made on the same cpu */

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