Commit 7ec27233 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next-4.12' of git://people.freedesktop.org/~agd5f/linux into drm-next 

Fixes for 4.12.  This is a bit bigger than usual since it's 3 weeks
worth of fixes and most of these changes are for vega10 which is
new for 4.12 and still in a fair amount of flux.  It looks like
you missed my last pull request, so those patches are included here
as well.  Highlights:
- Lots of vega10 fixes
- Fix interruptable wait mixup
- Fan control method fixes
- Misc display fixes for radeon and amdgpu
- Misc bug fixes

* 'drm-next-4.12' of git://people.freedesktop.org/~agd5f/linux: (132 commits)
  drm/amd/powerplay: refine pwm1_enable callback functions for CI.
  drm/amd/powerplay: refine pwm1_enable callback functions for vi.
  drm/amd/powerplay: refine pwm1_enable callback functions for Vega10.
  drm/amdgpu: refine amdgpu pwm1_enable sysfs interface.
  drm/amdgpu: add amd fan ctrl mode enums.
  drm/amd/powerplay: add more smu message on Vega10.
  drm/amdgpu: fix dependency issue
  drm/amd: fix init order of sched job
  drm/amdgpu: add some additional vega10 pci ids
  drm/amdgpu/soc15: use atomfirmware for setting bios scratch for reset
  drm/amdgpu/atomfirmware: add function to update engine hang status
  drm/radeon: only warn once in radeon_ttm_bo_destroy if va list not empty
  drm/amdgpu: fix mutex list null pointer reference
  drm/amd/powerplay: fix bug sclk/mclk level can't be set on vega10.
  drm/amd/powerplay: Setup sw CTF to allow graceful exit when temperature exceeds maximum.
  drm/amd/powerplay: delete dead code in powerplay.
  drm/amdgpu: Use less generic enum definitions
  drm/amdgpu/gfx9: derive tile pipes from golden settings
  drm/amdgpu/gfx: drop max_gs_waves_per_vgt
  drm/amd/powerplay: disable engine spread spectrum feature on Vega10.
  ...
parents bab1e2fe afa31879

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+9 −7
Original line number Original line Diff line number Diff line
@@ -110,6 +110,7 @@ extern int amdgpu_pos_buf_per_se; 
extern int amdgpu_cntl_sb_buf_per_se;

extern int amdgpu_cntl_sb_buf_per_se;

extern int amdgpu_param_buf_per_se;

extern int amdgpu_param_buf_per_se;





#define AMDGPU_DEFAULT_GTT_SIZE_MB		3072ULL /* 3GB by default */

#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS	        3000

#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS	        3000

#define AMDGPU_MAX_USEC_TIMEOUT			100000	/* 100 ms */

#define AMDGPU_MAX_USEC_TIMEOUT			100000	/* 100 ms */

#define AMDGPU_FENCE_JIFFIES_TIMEOUT		(HZ / 2)

#define AMDGPU_FENCE_JIFFIES_TIMEOUT		(HZ / 2)
@@ -966,6 +967,8 @@ struct amdgpu_gfx_config { 
	unsigned mc_arb_ramcfg;

	unsigned mc_arb_ramcfg;

	unsigned gb_addr_config;

	unsigned gb_addr_config;

	unsigned num_rbs;

	unsigned num_rbs;

	unsigned gs_vgt_table_depth;

	unsigned gs_prim_buffer_depth;





	uint32_t tile_mode_array[32];

	uint32_t tile_mode_array[32];

	uint32_t macrotile_mode_array[16];

	uint32_t macrotile_mode_array[16];
@@ -980,6 +983,7 @@ struct amdgpu_gfx_config { 
struct amdgpu_cu_info {

struct amdgpu_cu_info {

	uint32_t number; /* total active CU number */

	uint32_t number; /* total active CU number */

	uint32_t ao_cu_mask;

	uint32_t ao_cu_mask;

	uint32_t wave_front_size;

	uint32_t bitmap[4][4];

	uint32_t bitmap[4][4];

};

};
@@ -1000,10 +1004,10 @@ struct amdgpu_ngg_buf { 
};

};





enum {

enum {

	PRIM = 0,

	NGG_PRIM = 0,

	POS,

	NGG_POS,

	CNTL,

	NGG_CNTL,

	PARAM,

	NGG_PARAM,

	NGG_BUF_MAX

	NGG_BUF_MAX

};

};
@@ -1125,6 +1129,7 @@ struct amdgpu_job { 
	void			*owner;

	void			*owner;

	uint64_t		fence_ctx; /* the fence_context this job uses */

	uint64_t		fence_ctx; /* the fence_context this job uses */

	bool                    vm_needs_flush;

	bool                    vm_needs_flush;

	bool			need_pipeline_sync;

	unsigned		vm_id;

	unsigned		vm_id;

	uint64_t		vm_pd_addr;

	uint64_t		vm_pd_addr;

	uint32_t		gds_base, gds_size;

	uint32_t		gds_base, gds_size;
@@ -1704,9 +1709,6 @@ void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v); 
#define WREG32_FIELD_OFFSET(reg, offset, field, val)	\

#define WREG32_FIELD_OFFSET(reg, offset, field, val)	\

	WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))

	WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))





#define WREG32_FIELD15(ip, idx, reg, field, val)	\

	WREG32(SOC15_REG_OFFSET(ip, idx, mm##reg), (RREG32(SOC15_REG_OFFSET(ip, idx, mm##reg)) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))



/*

/*

 * BIOS helpers.

 * BIOS helpers.

 */

 */

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

+6 −0
Original line number Original line Diff line number Diff line
@@ -1727,6 +1727,12 @@ void amdgpu_atombios_scratch_regs_restore(struct amdgpu_device *adev) 
{

{

	int i;

	int i;





	/*

	 * VBIOS will check ASIC_INIT_COMPLETE bit to decide if

	 * execute ASIC_Init posting via driver

	 */

	adev->bios_scratch[7] &= ~ATOM_S7_ASIC_INIT_COMPLETE_MASK;



	for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++)

	for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++)

		WREG32(mmBIOS_SCRATCH_0 + i, adev->bios_scratch[i]);

		WREG32(mmBIOS_SCRATCH_0 + i, adev->bios_scratch[i]);

}

}

drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

+20 −0
Original line number Original line Diff line number Diff line
@@ -26,6 +26,7 @@ 
#include "atomfirmware.h"

#include "atomfirmware.h"

#include "amdgpu_atomfirmware.h"

#include "amdgpu_atomfirmware.h"

#include "atom.h"

#include "atom.h"

#include "atombios.h"





#define get_index_into_master_table(master_table, table_name) (offsetof(struct master_table, table_name) / sizeof(uint16_t))

#define get_index_into_master_table(master_table, table_name) (offsetof(struct master_table, table_name) / sizeof(uint16_t))
@@ -77,10 +78,29 @@ void amdgpu_atomfirmware_scratch_regs_restore(struct amdgpu_device *adev) 
{

{

	int i;

	int i;





	/*

	 * VBIOS will check ASIC_INIT_COMPLETE bit to decide if

	 * execute ASIC_Init posting via driver

	 */

	adev->bios_scratch[7] &= ~ATOM_S7_ASIC_INIT_COMPLETE_MASK;



	for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++)

	for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++)

		WREG32(adev->bios_scratch_reg_offset + i, adev->bios_scratch[i]);

		WREG32(adev->bios_scratch_reg_offset + i, adev->bios_scratch[i]);

}

}





void amdgpu_atomfirmware_scratch_regs_engine_hung(struct amdgpu_device *adev,

						  bool hung)

{

	u32 tmp = RREG32(adev->bios_scratch_reg_offset + 3);



	if (hung)

		tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;

	else

		tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;



	WREG32(adev->bios_scratch_reg_offset + 3, tmp);

}



int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev)

int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev)

{

{

	struct atom_context *ctx = adev->mode_info.atom_context;

	struct atom_context *ctx = adev->mode_info.atom_context;

drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -28,6 +28,8 @@ bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device *adev) 
void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev);

void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev);

void amdgpu_atomfirmware_scratch_regs_save(struct amdgpu_device *adev);

void amdgpu_atomfirmware_scratch_regs_save(struct amdgpu_device *adev);

void amdgpu_atomfirmware_scratch_regs_restore(struct amdgpu_device *adev);

void amdgpu_atomfirmware_scratch_regs_restore(struct amdgpu_device *adev);

void amdgpu_atomfirmware_scratch_regs_engine_hung(struct amdgpu_device *adev,

						  bool hung);

int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev);

int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev);





#endif
 
#endif

drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c

+7 −6
Original line number Original line Diff line number Diff line
@@ -117,8 +117,13 @@ static void amdgpu_benchmark_move(struct amdgpu_device *adev, unsigned size, 
	}

	}





out_cleanup:

out_cleanup:

	/* Check error value now. The value can be overwritten when clean up.*/

	if (r) {

		DRM_ERROR("Error while benchmarking BO move.\n");

	}



	if (sobj) {

	if (sobj) {

		r = amdgpu_bo_reserve(sobj, false);

		r = amdgpu_bo_reserve(sobj, true);

		if (likely(r == 0)) {

		if (likely(r == 0)) {

			amdgpu_bo_unpin(sobj);

			amdgpu_bo_unpin(sobj);

			amdgpu_bo_unreserve(sobj);

			amdgpu_bo_unreserve(sobj);
@@ -126,17 +131,13 @@ out_cleanup: 
		amdgpu_bo_unref(&sobj);

		amdgpu_bo_unref(&sobj);

	}

	}

	if (dobj) {

	if (dobj) {

		r = amdgpu_bo_reserve(dobj, false);

		r = amdgpu_bo_reserve(dobj, true);

		if (likely(r == 0)) {

		if (likely(r == 0)) {

			amdgpu_bo_unpin(dobj);

			amdgpu_bo_unpin(dobj);

			amdgpu_bo_unreserve(dobj);

			amdgpu_bo_unreserve(dobj);

		}

		}

		amdgpu_bo_unref(&dobj);

		amdgpu_bo_unref(&dobj);

	}

	}



	if (r) {

		DRM_ERROR("Error while benchmarking BO move.\n");

	}

}

}





void amdgpu_benchmark(struct amdgpu_device *adev, int test_number)

void amdgpu_benchmark(struct amdgpu_device *adev, int test_number)

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