Commit 7ebd3faa authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm 

Pull KVM updates from Paolo Bonzini:
 "First round of KVM updates for 3.14; PPC parts will come next week.

  Nothing major here, just bugfixes all over the place.  The most
  interesting part is the ARM guys' virtualized interrupt controller
  overhaul, which lets userspace get/set the state and thus enables
  migration of ARM VMs"

* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (67 commits)
  kvm: make KVM_MMU_AUDIT help text more readable
  KVM: s390: Fix memory access error detection
  KVM: nVMX: Update guest activity state field on L2 exits
  KVM: nVMX: Fix nested_run_pending on activity state HLT
  KVM: nVMX: Clean up handling of VMX-related MSRs
  KVM: nVMX: Add tracepoints for nested_vmexit and nested_vmexit_inject
  KVM: nVMX: Pass vmexit parameters to nested_vmx_vmexit
  KVM: nVMX: Leave VMX mode on clearing of feature control MSR
  KVM: VMX: Fix DR6 update on #DB exception
  KVM: SVM: Fix reading of DR6
  KVM: x86: Sync DR7 on KVM_SET_DEBUGREGS
  add support for Hyper-V reference time counter
  KVM: remove useless write to vcpu->hv_clock.tsc_timestamp
  KVM: x86: fix tsc catchup issue with tsc scaling
  KVM: x86: limit PIT timer frequency
  KVM: x86: handle invalid root_hpa everywhere
  kvm: Provide kvm_vcpu_eligible_for_directed_yield() stub
  kvm: vfio: silence GCC warning
  KVM: ARM: Remove duplicate include
  arm/arm64: KVM: relax the requirements of VMA alignment for THP
  ...
parents bb1281f2 7650b687

Documentation/virtual/kvm/api.txt

+9 −4
Original line number Diff line number Diff line
@@ -2104,7 +2104,7 @@ Returns: 0 on success, -1 on error 
Allows setting an eventfd to directly trigger a guest interrupt.

kvm_irqfd.fd specifies the file descriptor to use as the eventfd and

kvm_irqfd.gsi specifies the irqchip pin toggled by this event.  When

an event is tiggered on the eventfd, an interrupt is injected into

an event is triggered on the eventfd, an interrupt is injected into

the guest using the specified gsi pin.  The irqfd is removed using

the KVM_IRQFD_FLAG_DEASSIGN flag, specifying both kvm_irqfd.fd

and kvm_irqfd.gsi.
@@ -2115,7 +2115,7 @@ interrupts. When KVM_IRQFD_FLAG_RESAMPLE is set the user must pass an 
additional eventfd in the kvm_irqfd.resamplefd field.  When operating

in resample mode, posting of an interrupt through kvm_irq.fd asserts

the specified gsi in the irqchip.  When the irqchip is resampled, such

as from an EOI, the gsi is de-asserted and the user is notifed via

as from an EOI, the gsi is de-asserted and the user is notified via

kvm_irqfd.resamplefd.  It is the user's responsibility to re-queue

the interrupt if the device making use of it still requires service.

Note that closing the resamplefd is not sufficient to disable the
@@ -2327,7 +2327,7 @@ current state. "addr" is ignored. 
Capability: basic

Architectures: arm, arm64

Type: vcpu ioctl

Parameters: struct struct kvm_vcpu_init (in)

Parameters: struct kvm_vcpu_init (in)

Returns: 0 on success; -1 on error

Errors:

  EINVAL:    the target is unknown, or the combination of features is invalid.
@@ -2391,7 +2391,8 @@ struct kvm_reg_list { 
This ioctl returns the guest registers that are supported for the

KVM_GET_ONE_REG/KVM_SET_ONE_REG calls.



4.85 KVM_ARM_SET_DEVICE_ADDR



4.85 KVM_ARM_SET_DEVICE_ADDR (deprecated)



Capability: KVM_CAP_ARM_SET_DEVICE_ADDR

Architectures: arm, arm64
@@ -2429,6 +2430,10 @@ must be called after calling KVM_CREATE_IRQCHIP, but before calling 
KVM_RUN on any of the VCPUs.  Calling this ioctl twice for any of the

base addresses will return -EEXIST.



Note, this IOCTL is deprecated and the more flexible SET/GET_DEVICE_ATTR API

should be used instead.





4.86 KVM_PPC_RTAS_DEFINE_TOKEN



Capability: KVM_CAP_PPC_RTAS

Documentation/virtual/kvm/devices/arm-vgic.txt

0 → 100644
+73 −0
Original line number Diff line number Diff line 
ARM Virtual Generic Interrupt Controller (VGIC)

===============================================



Device types supported:

  KVM_DEV_TYPE_ARM_VGIC_V2     ARM Generic Interrupt Controller v2.0



Only one VGIC instance may be instantiated through either this API or the

legacy KVM_CREATE_IRQCHIP api.  The created VGIC will act as the VM interrupt

controller, requiring emulated user-space devices to inject interrupts to the

VGIC instead of directly to CPUs.



Groups:

  KVM_DEV_ARM_VGIC_GRP_ADDR

  Attributes:

    KVM_VGIC_V2_ADDR_TYPE_DIST (rw, 64-bit)

      Base address in the guest physical address space of the GIC distributor

      register mappings.



    KVM_VGIC_V2_ADDR_TYPE_CPU (rw, 64-bit)

      Base address in the guest physical address space of the GIC virtual cpu

      interface register mappings.



  KVM_DEV_ARM_VGIC_GRP_DIST_REGS

  Attributes:

    The attr field of kvm_device_attr encodes two values:

    bits:     | 63   ....  40 | 39 ..  32  |  31   ....    0 |

    values:   |    reserved   |   cpu id   |      offset     |



    All distributor regs are (rw, 32-bit)



    The offset is relative to the "Distributor base address" as defined in the

    GICv2 specs.  Getting or setting such a register has the same effect as

    reading or writing the register on the actual hardware from the cpu

    specified with cpu id field.  Note that most distributor fields are not

    banked, but return the same value regardless of the cpu id used to access

    the register.

  Limitations:

    - Priorities are not implemented, and registers are RAZ/WI

  Errors:

    -ENODEV: Getting or setting this register is not yet supported

    -EBUSY: One or more VCPUs are running



  KVM_DEV_ARM_VGIC_GRP_CPU_REGS

  Attributes:

    The attr field of kvm_device_attr encodes two values:

    bits:     | 63   ....  40 | 39 ..  32  |  31   ....    0 |

    values:   |    reserved   |   cpu id   |      offset     |



    All CPU interface regs are (rw, 32-bit)



    The offset specifies the offset from the "CPU interface base address" as

    defined in the GICv2 specs.  Getting or setting such a register has the

    same effect as reading or writing the register on the actual hardware.



    The Active Priorities Registers APRn are implementation defined, so we set a

    fixed format for our implementation that fits with the model of a "GICv2

    implementation without the security extensions" which we present to the

    guest.  This interface always exposes four register APR[0-3] describing the

    maximum possible 128 preemption levels.  The semantics of the register

    indicate if any interrupts in a given preemption level are in the active

    state by setting the corresponding bit.



    Thus, preemption level X has one or more active interrupts if and only if:



      APRn[X mod 32] == 0b1,  where n = X / 32



    Bits for undefined preemption levels are RAZ/WI.



  Limitations:

    - Priorities are not implemented, and registers are RAZ/WI

  Errors:

    -ENODEV: Getting or setting this register is not yet supported

    -EBUSY: One or more VCPUs are running

Documentation/virtual/kvm/hypercalls.txt

+4 −1
Original line number Diff line number Diff line
@@ -17,6 +17,9 @@ S390: 
  S390 uses diagnose instruction as hypercall (0x500) along with hypercall

  number in R1.



  For further information on the S390 diagnose call as supported by KVM,

  refer to Documentation/virtual/kvm/s390-diag.txt.



 PowerPC:

  It uses R3-R10 and hypercall number in R11. R4-R11 are used as output registers.

  Return value is placed in R3.
@@ -74,7 +77,7 @@ Usage example : A vcpu of a paravirtualized guest that is busywaiting in guest 
kernel mode for an event to occur (ex: a spinlock to become available) can

execute HLT instruction once it has busy-waited for more than a threshold

time-interval. Execution of HLT instruction would cause the hypervisor to put

the vcpu to sleep until occurence of an appropriate event. Another vcpu of the

the vcpu to sleep until occurrence of an appropriate event. Another vcpu of the

same guest can wakeup the sleeping vcpu by issuing KVM_HC_KICK_CPU hypercall,

specifying APIC ID (a1) of the vcpu to be woken up. An additional argument (a0)

is used in the hypercall for future use.

Documentation/virtual/kvm/locking.txt

+2 −2
Original line number Diff line number Diff line
@@ -112,7 +112,7 @@ The Dirty bit is lost in this case. 


In order to avoid this kind of issue, we always treat the spte as "volatile"

if it can be updated out of mmu-lock, see spte_has_volatile_bits(), it means,

the spte is always atomicly updated in this case.

the spte is always atomically updated in this case.



3): flush tlbs due to spte updated

If the spte is updated from writable to readonly, we should flush all TLBs,
@@ -125,7 +125,7 @@ be flushed caused by this reason in mmu_spte_update() since this is a common 
function to update spte (present -> present).



Since the spte is "volatile" if it can be updated out of mmu-lock, we always

atomicly update the spte, the race caused by fast page fault can be avoided,

atomically update the spte, the race caused by fast page fault can be avoided,

See the comments in spte_has_volatile_bits() and mmu_spte_update().



3. Reference

Documentation/virtual/kvm/ppc-pv.txt

+1 −1
Original line number Diff line number Diff line
@@ -115,7 +115,7 @@ If any other bit changes in the MSR, please still use mtmsr(d). 
Patched instructions

====================



The "ld" and "std" instructions are transormed to "lwz" and "stw" instructions

The "ld" and "std" instructions are transformed to "lwz" and "stw" instructions

respectively on 32 bit systems with an added offset of 4 to accommodate for big

endianness.

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