Commit 7e5b2db7 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus 

Pull MIPS updates from Ralf Baechle:
 "The whole series has been sitting in -next for quite a while with no
  complaints.  The last change to the series was before the weekend the
  removal of an SPI patch which Grant - even though previously acked by
  himself - appeared to raise objections.  So I removed it until the
  situation is clarified.  Other than that all the patches have the acks
  from their respective maintainers, all MIPS and x86 defconfigs are
  building fine and I'm not aware of any problems introduced by this
  series.

  Among the key features for this patch series is a sizable patchset for
  Lantiq which among other things introduces support for Lantiq's
  flagship product, the FALCON SOC.  It also means that the opensource
  developers behind this patchset have overtaken Lantiq's competing
  inhouse development team that was working behind closed doors.

  Less noteworthy the ath79 patchset which adds support for a few more
  chip variants, cleanups and fixes.  Finally the usual dose of tweaking
  of generic code."

Fix up trivial conflicts in arch/mips/lantiq/xway/gpio_{ebu,stp}.c where
printk spelling fixes clashed with file move and eventual removal of the
printk.

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (81 commits)
  MIPS: lantiq: remove orphaned code
  MIPS: Remove all -Wall and almost all -Werror usage from arch/mips.
  MIPS: lantiq: implement support for FALCON soc
  MTD: MIPS: lantiq: verify that the NOR interface is available on falcon soc
  MTD: MIPS: lantiq: implement OF support
  watchdog: MIPS: lantiq: implement OF support and minor fixes
  SERIAL: MIPS: lantiq: implement OF support
  GPIO: MIPS: lantiq: convert gpio-stp-xway to OF
  GPIO: MIPS: lantiq: convert gpio-mm-lantiq to OF and of_mm_gpio
  GPIO: MIPS: lantiq: move gpio-stp and gpio-ebu to the subsystem folder
  MIPS: pci: convert lantiq driver to OF
  MIPS: lantiq: convert dma to platform driver
  MIPS: lantiq: implement support for clkdev api
  MIPS: lantiq: drop ltq_gpio_request() and gpio_to_irq()
  OF: MIPS: lantiq: implement irq_domain support
  OF: MIPS: lantiq: implement OF support
  MIPS: lantiq: drop mips_machine support
  OF: PCI: const usage needed by MIPS
  MIPS: Cavium: Remove smp_reserve_lock.
  MIPS: Move cache setup to setup_arch().
  ...
parents 227d1e43 c819baf3

Documentation/devicetree/bindings/gpio/gpio-mm-lantiq.txt

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+38 −0
Original line number Diff line number Diff line 
Lantiq SoC External Bus memory mapped GPIO controller



By attaching hardware latches to the EBU it is possible to create output

only gpios. This driver configures a special memory address, which when

written to outputs 16 bit to the latches.



The node describing the memory mapped GPIOs needs to be a child of the node

describing the "lantiq,localbus".



Required properties:

- compatible : Should be "lantiq,gpio-mm-lantiq"

- reg : Address and length of the register set for the device

- #gpio-cells : Should be two.  The first cell is the pin number and

  the second cell is used to specify optional parameters (currently

  unused).

- gpio-controller : Marks the device node as a gpio controller.



Optional properties:

- lantiq,shadow : The default value that we shall assume as already set on the

  shift register cascade.



Example:



localbus@0 {

	#address-cells = <2>;

	#size-cells = <1>;

	ranges = <0 0 0x0 0x3ffffff /* addrsel0 */

		1 0 0x4000000 0x4000010>; /* addsel1 */

	compatible = "lantiq,localbus", "simple-bus";



	gpio_mm0: gpio@4000000 {

		compatible = "lantiq,gpio-mm";

		reg = <1 0x0 0x10>;

		gpio-controller;

		#gpio-cells = <2>;

		lantiq,shadow = <0x77f>

	};

}

Documentation/devicetree/bindings/gpio/gpio-stp-xway.txt

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+42 −0
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Lantiq SoC Serial To Parallel (STP) GPIO controller



The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a

peripheral controller used to drive external shift register cascades. At most

3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem

to drive the 2 LSBs of the cascade automatically.





Required properties:

- compatible : Should be "lantiq,gpio-stp-xway"

- reg : Address and length of the register set for the device

- #gpio-cells : Should be two.  The first cell is the pin number and

  the second cell is used to specify optional parameters (currently

  unused).

- gpio-controller : Marks the device node as a gpio controller.



Optional properties:

- lantiq,shadow : The default value that we shall assume as already set on the

  shift register cascade.

- lantiq,groups : Set the 3 bit mask to select which of the 3 groups are enabled

  in the shift register cascade.

- lantiq,dsl : The dsl core can control the 2 LSBs of the gpio cascade. This 2 bit

  property can enable this feature.

- lantiq,phy1 : The gphy1 core can control 3 bits of the gpio cascade.

- lantiq,phy2 : The gphy2 core can control 3 bits of the gpio cascade.

- lantiq,rising : use rising instead of falling edge for the shift register



Example:



gpio1: stp@E100BB0 {

	compatible = "lantiq,gpio-stp-xway";

	reg = <0xE100BB0 0x40>;

	#gpio-cells = <2>;

	gpio-controller;



	lantiq,shadow = <0xffff>;

	lantiq,groups = <0x7>;

	lantiq,dsl = <0x3>;

	lantiq,phy1 = <0x7>;

	lantiq,phy2 = <0x7>;

	/* lantiq,rising; */

};

arch/mips/Kconfig

+9 −6
Original line number Diff line number Diff line
@@ -233,8 +233,9 @@ config LANTIQ 
	select ARCH_REQUIRE_GPIOLIB

	select SWAP_IO_SPACE

	select BOOT_RAW

	select HAVE_CLK

	select MIPS_MACHINE

	select HAVE_MACH_CLKDEV

	select CLKDEV_LOOKUP

	select USE_OF



config LASAT

	bool "LASAT Networks platforms"
@@ -1783,10 +1784,12 @@ endchoice 


config FORCE_MAX_ZONEORDER

	int "Maximum zone order"

	range 13 64 if SYS_SUPPORTS_HUGETLBFS && PAGE_SIZE_32KB

	default "13" if SYS_SUPPORTS_HUGETLBFS && PAGE_SIZE_32KB

	range 12 64 if SYS_SUPPORTS_HUGETLBFS && PAGE_SIZE_16KB

	default "12" if SYS_SUPPORTS_HUGETLBFS && PAGE_SIZE_16KB

	range 14 64 if HUGETLB_PAGE && PAGE_SIZE_64KB

	default "14" if HUGETLB_PAGE && PAGE_SIZE_64KB

	range 13 64 if HUGETLB_PAGE && PAGE_SIZE_32KB

	default "13" if HUGETLB_PAGE && PAGE_SIZE_32KB

	range 12 64 if HUGETLB_PAGE && PAGE_SIZE_16KB

	default "12" if HUGETLB_PAGE && PAGE_SIZE_16KB

	range 11 64

	default "11"

	help

arch/mips/alchemy/devboards/db1200.c

+1 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ 
#include <linux/gpio.h>

#include <linux/i2c.h>

#include <linux/init.h>

#include <linux/module.h>

#include <linux/interrupt.h>

#include <linux/io.h>

#include <linux/leds.h>

arch/mips/ath79/Kconfig

+24 −1
Original line number Diff line number Diff line
@@ -26,6 +26,18 @@ config ATH79_MACH_AP81 
	  Say 'Y' here if you want your kernel to support the

	  Atheros AP81 reference board.



config ATH79_MACH_DB120

	bool "Atheros DB120 reference board"

	select SOC_AR934X

	select ATH79_DEV_GPIO_BUTTONS

	select ATH79_DEV_LEDS_GPIO

	select ATH79_DEV_SPI

	select ATH79_DEV_USB

	select ATH79_DEV_WMAC

	help

	  Say 'Y' here if you want your kernel to support the

	  Atheros DB120 reference board.



config ATH79_MACH_PB44

	bool "Atheros PB44 reference board"

	select SOC_AR71XX
@@ -52,12 +64,14 @@ endmenu 
config SOC_AR71XX

	select USB_ARCH_HAS_EHCI

	select USB_ARCH_HAS_OHCI

	select HW_HAS_PCI

	def_bool n



config SOC_AR724X

	select USB_ARCH_HAS_EHCI

	select USB_ARCH_HAS_OHCI

	select HW_HAS_PCI

	select PCI_AR724X if PCI

	def_bool n



config SOC_AR913X
@@ -68,6 +82,15 @@ config SOC_AR933X 
	select USB_ARCH_HAS_EHCI

	def_bool n



config SOC_AR934X

	select USB_ARCH_HAS_EHCI

	select HW_HAS_PCI

	select PCI_AR724X if PCI

	def_bool n



config PCI_AR724X

	def_bool n



config ATH79_DEV_GPIO_BUTTONS

	def_bool n
@@ -81,7 +104,7 @@ config ATH79_DEV_USB 
	def_bool n



config ATH79_DEV_WMAC

	depends on (SOC_AR913X || SOC_AR933X)

	depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X)

	def_bool n



endif

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