Commit 7e5b22dd authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'remotes/lorenzo/pci/endpoint' 

  - Use memcpy_fromio()/memcpy_toio() instead of plain memcpy() in PCI
    endpoint framework (Wen Yang)

  - Add interface to discover supported endpoint features to replace a
    bitfield that wasn't flexible enough (Kishon Vijay Abraham I)

  - Implement the new supported-feature interface for designware-plat,
    dra7xx, rockchip, cadence (Kishon Vijay Abraham I)

  - Fix issues with 64-bit BAR in endpoints (Kishon Vijay Abraham I)

  - Add layerscape endpoint mode support (Xiaowei Bao)

* remotes/lorenzo/pci/endpoint:
  misc: pci_endpoint_test: Add the layerscape EP device support
  PCI: layerscape: Add EP mode support
  arm64: dts: Add the PCIE EP node in dts
  dt-bindings: add DT binding for the layerscape PCIe controller with EP mode
  PCI: endpoint: Remove features member in struct pci_epc
  PCI: designware-plat: Remove setting epc->features in Designware plat EP driver
  PCI: rockchip: Remove pci_epf_linkup() from Rockchip EP driver
  PCI: cadence: Remove pci_epf_linkup() from Cadence EP driver
  PCI: pci-epf-test: Use pci_epc_get_features() to get EPC features
  PCI: pci-epf-test: Do not allocate next BARs memory if current BAR is 64Bit
  PCI: pci-epf-test: Remove setting epf_bar flags in function driver
  PCI: endpoint: Fix pci_epf_alloc_space() to set correct MEM TYPE flags
  PCI: endpoint: Add helper to get first unreserved BAR
  PCI: cadence: Populate ->get_features() cdns_pcie_epc_ops
  PCI: rockchip: Populate ->get_features() dw_pcie_ep_ops
  PCI: pci-dra7xx: Populate ->get_features() dw_pcie_ep_ops
  PCI: designware-plat: Populate ->get_features() dw_pcie_ep_ops
  PCI: dwc: Add ->get_features() callback function to dw_pcie_ep_ops
  PCI: endpoint: Add new pci_epc_ops to get EPC features
  PCI: endpoint: functions: Use memcpy_fromio()/memcpy_toio()
parents 2506419e 85cef374

Documentation/devicetree/bindings/pci/layerscape-pci.txt

+3 −0
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ information. 


Required properties:

- compatible: should contain the platform identifier such as:

  RC mode:

        "fsl,ls1021a-pcie"

        "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"

        "fsl,ls2088a-pcie"
@@ -20,6 +21,8 @@ Required properties: 
        "fsl,ls1046a-pcie"

        "fsl,ls1043a-pcie"

        "fsl,ls1012a-pcie"

  EP mode:

	"fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"

- reg: base addresses and lengths of the PCIe controller register blocks.

- interrupts: A list of interrupt outputs of the controller. Must contain an

  entry for each entry in the interrupt-names property.

arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi

+33 −1
Original line number Diff line number Diff line
@@ -657,6 +657,17 @@ 
			status = "disabled";

		};



		pcie_ep@3400000 {

			compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";

			reg = <0x00 0x03400000 0x0 0x00100000

				0x40 0x00000000 0x8 0x00000000>;

			reg-names = "regs", "addr_space";

			num-ib-windows = <6>;

			num-ob-windows = <8>;

			num-lanes = <2>;

			status = "disabled";

		};



		pcie@3500000 {

			compatible = "fsl,ls1046a-pcie";

			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
@@ -683,6 +694,17 @@ 
			status = "disabled";

		};



		pcie_ep@3500000 {

			compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";

			reg = <0x00 0x03500000 0x0 0x00100000

				0x48 0x00000000 0x8 0x00000000>;

			reg-names = "regs", "addr_space";

			num-ib-windows = <6>;

			num-ob-windows = <8>;

			num-lanes = <2>;

			status = "disabled";

		};



		pcie@3600000 {

			compatible = "fsl,ls1046a-pcie";

			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
@@ -709,6 +731,17 @@ 
			status = "disabled";

		};



		pcie_ep@3600000 {

			compatible = "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep";

			reg = <0x00 0x03600000 0x0 0x00100000

				0x50 0x00000000 0x8 0x00000000>;

			reg-names = "regs", "addr_space";

			num-ib-windows = <6>;

			num-ob-windows = <8>;

			num-lanes = <2>;

			status = "disabled";

		};



		qdma: dma-controller@8380000 {

			compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma";

			reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
@@ -729,7 +762,6 @@ 
			queue-sizes = <64 64>;

			big-endian;

		};



	};



	reserved-memory {

drivers/misc/pci_endpoint_test.c

+1 −0
Original line number Diff line number Diff line
@@ -788,6 +788,7 @@ static void pci_endpoint_test_remove(struct pci_dev *pdev) 
static const struct pci_device_id pci_endpoint_test_tbl[] = {

	{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x) },

	{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x) },

	{ PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0x81c0) },

	{ PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS, 0xedda) },

	{ }

};

drivers/pci/controller/dwc/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -8,7 +8,7 @@ obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o 
obj-$(CONFIG_PCI_IMX6) += pci-imx6.o

obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o

obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone.o

obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o

obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o pci-layerscape-ep.o

obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o

obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o

obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o

drivers/pci/controller/dwc/pci-dra7xx.c

+13 −0
Original line number Diff line number Diff line
@@ -394,9 +394,22 @@ static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no, 
	return 0;

}



static const struct pci_epc_features dra7xx_pcie_epc_features = {

	.linkup_notifier = true,

	.msi_capable = true,

	.msix_capable = false,

};



static const struct pci_epc_features*

dra7xx_pcie_get_features(struct dw_pcie_ep *ep)

{

	return &dra7xx_pcie_epc_features;

}



static struct dw_pcie_ep_ops pcie_ep_ops = {

	.ep_init = dra7xx_pcie_ep_init,

	.raise_irq = dra7xx_pcie_raise_irq,

	.get_features = dra7xx_pcie_get_features,

};



static int __init dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx,

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