Commit 7e21774d authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'clk-for-linus-3.14-part1' of git://git.linaro.org/people/mike.turquette/linux 

Pull clk framework changes from Mike Turquette:
 "The first half of the clk framework pull request is made up almost
  entirely of new platform/driver support.  There are some conversions
  of existing drivers to the common-clock Device Tree binding, and a few
  non-critical fixes to the framework.

  Due to an entirely unnecessary cyclical dependency with the arm-soc
  tree this pull request is broken into two pieces.  The second piece
  will be sent out after arm-soc sends you the pull request that merged
  in core support for the HiSilicon 3620 platform.  That same pull
  request from arm-soc depends on this pull request to merge in those
  HiSilicon bits without causing build failures"

[ Just did the ARM SoC merges, so getting ready for the second clk tree
  pull request   - Linus ]

* tag 'clk-for-linus-3.14-part1' of git://git.linaro.org/people/mike.turquette/linux: (97 commits)
  devicetree: bindings: Document qcom,mmcc
  devicetree: bindings: Document qcom,gcc
  clk: qcom: Add support for MSM8660's global clock controller (GCC)
  clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC)
  clk: qcom: Add support for MSM8974's global clock controller (GCC)
  clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC)
  clk: qcom: Add support for MSM8960's global clock controller (GCC)
  clk: qcom: Add reset controller support
  clk: qcom: Add support for branches/gate clocks
  clk: qcom: Add support for root clock generators (RCGs)
  clk: qcom: Add support for phase locked loops (PLLs)
  clk: qcom: Add a regmap type clock struct
  clk: Add set_rate_and_parent() op
  reset: Silence warning in reset-controller.h
  clk: sirf: re-arch to make the codes support both prima2 and atlas6
  clk: composite: pass mux_hw into determine_rate
  clk: shmobile: Fix MSTP clock array initialization
  clk: shmobile: Fix MSTP clock index
  ARM: dts: Add clock provider specific properties to max77686 node
  clk: max77686: Register OF clock provider
  ...
parents 0ba3307a 2e84d751

Documentation/clk.txt

+7 −0
Original line number Diff line number Diff line
@@ -77,6 +77,11 @@ the operations defined in clk.h: 
		int		(*set_parent)(struct clk_hw *hw, u8 index);

		u8		(*get_parent)(struct clk_hw *hw);

		int		(*set_rate)(struct clk_hw *hw, unsigned long);

		int		(*set_rate_and_parent)(struct clk_hw *hw,

					    unsigned long rate,

					    unsigned long parent_rate, u8 index);

		unsigned long	(*recalc_accuracy)(struct clk_hw *hw,

						   unsigned long parent_accuracy);

		void		(*init)(struct clk_hw *hw);

	};
@@ -202,6 +207,8 @@ optional or must be evaluated on a case-by-case basis. 
.set_parent     |      |             | n             | y           | n    |

.get_parent     |      |             | n             | y           | n    |

                |      |             |               |             |      |

.recalc_accuracy|      |             |               |             |      |

                |      |             |               |             |      |

.init           |      |             |               |             |      |

                -----------------------------------------------------------

[1] either one of round_rate or determine_rate is required.

Documentation/devicetree/bindings/clock/clk-exynos-audss.txt

+35 −4
Original line number Diff line number Diff line
@@ -8,12 +8,29 @@ Required Properties: 


- compatible: should be one of the following:

  - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.

  - "samsung,exynos5250-audss-clock" - controller compatible with all Exynos5 SoCs.



  - "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250

    SoCs.

  - "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420

    SoCs.

- reg: physical base address and length of the controller's register set.



- #clock-cells: should be 1.



- clocks:

  - pll_ref: Fixed rate PLL reference clock, parent of mout_audss. "fin_pll"

    is used if not specified.

  - pll_in: Input PLL to the AudioSS block, parent of mout_audss. "fout_epll"

    is used if not specified.

  - cdclk: External i2s clock, parent of mout_i2s. "cdclk0" is used if not

    specified.

  - sclk_audio: Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if

    not specified.

  - sclk_pcm_in: PCM clock, parent of sclk_pcm.  "sclk_pcm0" is used if not

    specified.



- clock-names: Aliases for the above clocks. They should be "pll_ref",

  "pll_in", "cdclk", "sclk_audio", and "sclk_pcm_in" respectively.



The following is the list of clocks generated by the controller. Each clock is

assigned an identifier and client nodes use this identifier to specify the

clock which they consume. Some of the clocks are available only on a particular
@@ -34,16 +51,30 @@ i2s_bus 6 
sclk_i2s        7

pcm_bus         8

sclk_pcm        9

adma            10      Exynos5420



Example 1: An example of a clock controller node using the default input

	   clock names is listed below.



clock_audss: audss-clock-controller@3810000 {

	compatible = "samsung,exynos5250-audss-clock";

	reg = <0x03810000 0x0C>;

	#clock-cells = <1>;

};



Example 1: An example of a clock controller node is listed below.

Example 2: An example of a clock controller node with the input clocks

           specified.



clock_audss: audss-clock-controller@3810000 {

	compatible = "samsung,exynos5250-audss-clock";

	reg = <0x03810000 0x0C>;

	#clock-cells = <1>;

	clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>,

		<&ext_i2s_clk>;

	clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk";

};



Example 2: I2S controller node that consumes the clock generated by the clock

Example 3: I2S controller node that consumes the clock generated by the clock

           controller. Refer to the standard clock bindings for information

           about 'clocks' and 'clock-names' property.

Documentation/devicetree/bindings/clock/emev2-clock.txt

0 → 100644
+98 −0
Original line number Diff line number Diff line 
Device tree Clock bindings for Renesas EMMA Mobile EV2



This binding uses the common clock binding.



* SMU

System Management Unit described in user's manual R19UH0037EJ1000_SMU.

This is not a clock provider, but clocks under SMU depend on it.



Required properties:

- compatible: Should be "renesas,emev2-smu"

- reg: Address and Size of SMU registers



* SMU_CLKDIV

Function block with an input mux and a divider, which corresponds to

"Serial clock generator" in fig."Clock System Overview" of the manual,

and "xxx frequency division setting register" (XXXCLKDIV) registers.

This makes internal (neither input nor output) clock that is provided

to input of xxxGCLK block.



Required properties:

- compatible: Should be "renesas,emev2-smu-clkdiv"

- reg: Byte offset from SMU base and Bit position in the register

- clocks: Parent clocks. Input clocks as described in clock-bindings.txt

- #clock-cells: Should be <0>



* SMU_GCLK

Clock gating node shown as "Clock stop processing block" in the

fig."Clock System Overview" of the manual.

Registers are "xxx clock gate control register" (XXXGCLKCTRL).



Required properties:

- compatible: Should be "renesas,emev2-smu-gclk"

- reg: Byte offset from SMU base and Bit position in the register

- clocks: Input clock as described in clock-bindings.txt

- #clock-cells: Should be <0>



Example of provider:



usia_u0_sclkdiv: usia_u0_sclkdiv {

	compatible = "renesas,emev2-smu-clkdiv";

	reg = <0x610 0>;

	clocks = <&pll3_fo>, <&pll4_fo>, <&pll1_fo>, <&osc1_fo>;

	#clock-cells = <0>;

};



usia_u0_sclk: usia_u0_sclk {

	compatible = "renesas,emev2-smu-gclk";

	reg = <0x4a0 1>;

	clocks = <&usia_u0_sclkdiv>;

	#clock-cells = <0>;

};



Example of consumer:



uart@e1020000 {

	compatible = "renesas,em-uart";

	reg = <0xe1020000 0x38>;

	interrupts = <0 8 0>;

	clocks = <&usia_u0_sclk>;

	clock-names = "sclk";

};



Example of clock-tree description:



 This describes a clock path in the clock tree

  c32ki -> pll3_fo -> usia_u0_sclkdiv -> usia_u0_sclk



smu@e0110000 {

	compatible = "renesas,emev2-smu";

	reg = <0xe0110000 0x10000>;

	#address-cells = <2>;

	#size-cells = <0>;



	c32ki: c32ki {

		compatible = "fixed-clock";

		clock-frequency = <32768>;

		#clock-cells = <0>;

	};

	pll3_fo: pll3_fo {

		compatible = "fixed-factor-clock";

		clocks = <&c32ki>;

		clock-div = <1>;

		clock-mult = <7000>;

		#clock-cells = <0>;

	};

	usia_u0_sclkdiv: usia_u0_sclkdiv {

		compatible = "renesas,emev2-smu-clkdiv";

		reg = <0x610 0>;

		clocks = <&pll3_fo>;

		#clock-cells = <0>;

	};

	usia_u0_sclk: usia_u0_sclk {

		compatible = "renesas,emev2-smu-gclk";

		reg = <0x4a0 1>;

		clocks = <&usia_u0_sclkdiv>;

		#clock-cells = <0>;

	};

};

Documentation/devicetree/bindings/clock/exynos5250-clock.txt

+1 −0
Original line number Diff line number Diff line
@@ -62,6 +62,7 @@ clock which they consume. 
  div_i2s1		157

  div_i2s2		158

  sclk_hdmiphy		159

  div_pcm0		160





   [Peripheral Clock Gates]

Documentation/devicetree/bindings/clock/fixed-clock.txt

+3 −0
Original line number Diff line number Diff line
@@ -10,6 +10,8 @@ Required properties: 
- clock-frequency : frequency of clock in Hz. Should be a single cell.



Optional properties:

- clock-accuracy : accuracy of clock in ppb (parts per billion).

		   Should be a single cell.

- gpios : From common gpio binding; gpio connection to clock enable pin.

- clock-output-names : From common clock binding.
@@ -18,4 +20,5 @@ Example: 
		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <1000000000>;

		clock-accuracy = <100>;

	};

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