Commit 7e14f223 authored by Thierry Reding's avatar Thierry Reding
Browse files

clk: tegra: Constify peripheral clock registers 



The peripheral clock registers are defined in static tables. These
tables never need to be modified at runtime, so they can reside in
read-only memory.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 3358d2d9

drivers/clk/tegra/clk-periph-gate.c

+1 −1
Original line number Diff line number Diff line
@@ -134,7 +134,7 @@ struct clk *tegra_clk_register_periph_gate(const char *name, 
	struct tegra_clk_periph_gate *gate;

	struct clk *clk;

	struct clk_init_data init;

	struct tegra_clk_periph_regs *pregs;

	const struct tegra_clk_periph_regs *pregs;



	pregs = get_reg_bank(clk_num);

	if (!pregs)

drivers/clk/tegra/clk-periph.c

+1 −1
Original line number Diff line number Diff line
@@ -145,7 +145,7 @@ static struct clk *_tegra_clk_register_periph(const char *name, 
{

	struct clk *clk;

	struct clk_init_data init;

	struct tegra_clk_periph_regs *bank;

	const struct tegra_clk_periph_regs *bank;

	bool div = !(periph->gate.flags & TEGRA_PERIPH_NO_DIV);



	if (periph->gate.flags & TEGRA_PERIPH_NO_DIV) {

drivers/clk/tegra/clk-tegra-periph.c

+1 −1
Original line number Diff line number Diff line
@@ -877,7 +877,7 @@ static void __init periph_clk_init(void __iomem *clk_base, 
	struct clk **dt_clk;



	for (i = 0; i < ARRAY_SIZE(periph_clks); i++) {

		struct tegra_clk_periph_regs *bank;

		const struct tegra_clk_periph_regs *bank;

		struct tegra_periph_init_data *data;



		data = periph_clks + i;

drivers/clk/tegra/clk.c

+2 −2
Original line number Diff line number Diff line
@@ -84,7 +84,7 @@ static int (*special_reset_assert)(unsigned long); 
static int (*special_reset_deassert)(unsigned long);

static unsigned int num_special_reset;



static struct tegra_clk_periph_regs periph_regs[] = {

static const struct tegra_clk_periph_regs periph_regs[] = {

	[0] = {

		.enb_reg = CLK_OUT_ENB_L,

		.enb_set_reg = CLK_OUT_ENB_SET_L,
@@ -182,7 +182,7 @@ static int tegra_clk_rst_deassert(struct reset_controller_dev *rcdev, 
	return -EINVAL;

}



struct tegra_clk_periph_regs *get_reg_bank(int clkid)

const struct tegra_clk_periph_regs *get_reg_bank(int clkid)

{

	int reg_bank = clkid / 32;

drivers/clk/tegra/clk.h

+2 −2
Original line number Diff line number Diff line
@@ -496,7 +496,7 @@ struct tegra_clk_periph_gate { 
	u8			flags;

	int			clk_num;

	int			*enable_refcnt;

	struct tegra_clk_periph_regs	*regs;

	const struct tegra_clk_periph_regs *regs;

};



#define to_clk_periph_gate(_hw)					\
@@ -716,7 +716,7 @@ void tegra_init_from_table(struct tegra_clk_init_table *tbl, 
void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,

		struct clk *clks[], int clk_max);



struct tegra_clk_periph_regs *get_reg_bank(int clkid);

const struct tegra_clk_periph_regs *get_reg_bank(int clkid);

struct clk **tegra_clk_init(void __iomem *clk_base, int num, int periph_banks);



struct clk **tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk);

CRA Git | Maintained and supported by SUSTech CRA and CCSE