drm/amdgpu: code cleanup around gpu reset (7dd8c205) · Commits · 戴 / test

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+4 −10

Original line number	Diff line number	Diff line
		@@ -4130,7 +4130,8 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
		struct amdgpu_job *job)
		{
		struct list_head device_list, *device_list_handle = NULL;
		bool need_full_reset, job_signaled;
		bool need_full_reset = false;
		bool job_signaled = false;
		struct amdgpu_hive_info *hive = NULL;
		struct amdgpu_device *tmp_adev = NULL;
		int i, r = 0;
		@@ -4151,13 +4152,9 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
		emergency_restart();
		}

		need_full_reset = job_signaled = false;

		dev_info(adev->dev, "GPU %s begin!\n",
		(in_ras_intr && !use_baco) ? "jobs stop":"reset");

		hive = amdgpu_get_xgmi_hive(adev, true);

		/*
		* Here we trylock to avoid chain of resets executing from
		* either trigger by jobs on different adevs in XGMI hive or jobs on
		@@ -4165,7 +4162,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
		* We always reset all schedulers for device and all devices for XGMI
		* hive so that should take care of them too.
		*/

		hive = amdgpu_get_xgmi_hive(adev, true);
		if (hive && !mutex_trylock(&hive->reset_lock)) {
		DRM_INFO("Bailing on TDR for s_job:%llx, hive: %llx as another already in progress",
		job ? job->base.id : -1, hive->hive_id);
		@@ -4232,7 +4229,6 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
		}
		}


		if (in_ras_intr && !use_baco)
		goto skip_sched_resume;

		@@ -4243,10 +4239,8 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
		* job->base holds a reference to parent fence
		*/
		if (job && job->base.s_fence->parent &&
		dma_fence_is_signaled(job->base.s_fence->parent))
		dma_fence_is_signaled(job->base.s_fence->parent)) {
		job_signaled = true;

		if (job_signaled) {
		dev_info(adev->dev, "Guilty job already signaled, skipping HW reset");
		goto skip_hw_reset;
		}

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