Commit 7dd09a1a authored by Xenia Ragiadakou's avatar Xenia Ragiadakou Committed by Sarah Sharp
Browse files

xhci: replace xhci_write_64() with writeq() 



Function xhci_write_64() is used to write 64bit xHC registers residing in MMIO.
On 32bit systems, xHC registers need to be written with 32bit accesses by
writing first the lower 32bits and then the higher 32bits. The header file
asm-generic/io-64-nonatomic-lo-hi.h ensures that on 32bit systems writeq() will
will write 64bit registers in 32bit chunks with low-high order.

Replace all calls to xhci_write_64() with calls to writeq().

This is done to reduce code duplication since 64bit low-high write logic
is already implemented and to take advantage of inherent "atomic" 64bit
write operations on 64bit systems.

Signed-off-by: default avatarXenia Ragiadakou <burzalodowa@gmail.com>
Signed-off-by: default avatarSarah Sharp <sarah.a.sharp@linux.intel.com>
parent e8b37332

drivers/usb/host/xhci-mem.c

+4 −4
Original line number Diff line number Diff line
@@ -1967,7 +1967,7 @@ static void xhci_set_hc_event_deq(struct xhci_hcd *xhci) 
	xhci_dbg_trace(xhci, trace_xhci_dbg_init,

			"// Write event ring dequeue pointer, "

			"preserving EHB bit");

	xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,

	writeq(((u64) deq & (u64) ~ERST_PTR_MASK) | temp,

			&xhci->ir_set->erst_dequeue);

}
@@ -2269,7 +2269,7 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags) 
	xhci_dbg_trace(xhci, trace_xhci_dbg_init,

			"// Device context base array address = 0x%llx (DMA), %p (virt)",

			(unsigned long long)xhci->dcbaa->dma, xhci->dcbaa);

	xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr);

	writeq(dma, &xhci->op_regs->dcbaa_ptr);



	/*

	 * Initialize the ring segment pool.  The ring must be a contiguous
@@ -2318,7 +2318,7 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags) 
		xhci->cmd_ring->cycle_state;

	xhci_dbg_trace(xhci, trace_xhci_dbg_init,

			"// Setting command ring address to 0x%x", val);

	xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);

	writeq(val_64, &xhci->op_regs->cmd_ring);

	xhci_dbg_cmd_ptrs(xhci);



	xhci->lpm_command = xhci_alloc_command(xhci, true, true, flags);
@@ -2399,7 +2399,7 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags) 
	val_64 = readq(&xhci->ir_set->erst_base);

	val_64 &= ERST_PTR_MASK;

	val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK);

	xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base);

	writeq(val_64, &xhci->ir_set->erst_base);



	/* Set the event ring dequeue address */

	xhci_set_hc_event_deq(xhci);

drivers/usb/host/xhci-ring.c

+3 −5
Original line number Diff line number Diff line
@@ -319,8 +319,7 @@ static int xhci_abort_cmd_ring(struct xhci_hcd *xhci) 
		return 0;

	}

	xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;

	xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,

			&xhci->op_regs->cmd_ring);

	writeq(temp_64 | CMD_RING_ABORT, &xhci->op_regs->cmd_ring);



	/* Section 4.6.1.2 of xHCI 1.0 spec says software should

	 * time the completion od all xHCI commands, including
@@ -2872,8 +2871,7 @@ hw_died: 
		 * the event ring should be empty.

		 */

		temp_64 = readq(&xhci->ir_set->erst_dequeue);

		xhci_write_64(xhci, temp_64 | ERST_EHB,

				&xhci->ir_set->erst_dequeue);

		writeq(temp_64 | ERST_EHB, &xhci->ir_set->erst_dequeue);

		spin_unlock(&xhci->lock);



		return IRQ_HANDLED;
@@ -2900,7 +2898,7 @@ hw_died: 


	/* Clear the event handler busy flag (RW1C); event ring is empty. */

	temp_64 |= ERST_EHB;

	xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);

	writeq(temp_64, &xhci->ir_set->erst_dequeue);



	spin_unlock(&xhci->lock);

drivers/usb/host/xhci.c

+4 −4
Original line number Diff line number Diff line
@@ -762,11 +762,11 @@ static void xhci_restore_registers(struct xhci_hcd *xhci) 
{

	writel(xhci->s3.command, &xhci->op_regs->command);

	writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);

	xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);

	writeq(xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);

	writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);

	writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);

	xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);

	xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);

	writeq(xhci->s3.erst_base, &xhci->ir_set->erst_base);

	writeq(xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);

	writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);

	writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);

}
@@ -785,7 +785,7 @@ static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci) 
	xhci_dbg_trace(xhci, trace_xhci_dbg_init,

			"// Setting command ring address to 0x%llx",

			(long unsigned long) val_64);

	xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);

	writeq(val_64, &xhci->op_regs->cmd_ring);

}



/*

drivers/usb/host/xhci.h

+9 −20
Original line number Diff line number Diff line
@@ -28,6 +28,15 @@ 
#include <linux/kernel.h>

#include <linux/usb/hcd.h>



/*

 * Registers should always be accessed with double word or quad word accesses.

 *

 * Some xHCI implementations may support 64-bit address pointers.  Registers

 * with 64-bit address pointers should be written to with dword accesses by

 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.

 * xHCI implementations that do not support 64-bit address pointers will ignore

 * the high dword, and write order is irrelevant.

 */

#include <asm-generic/io-64-nonatomic-lo-hi.h>



/* Code sharing between pci-quirks and xhci hcd */
@@ -1597,26 +1606,6 @@ static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) 
#define xhci_warn_ratelimited(xhci, fmt, args...) \

	dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)



/*

 * Registers should always be accessed with double word or quad word accesses.

 *

 * Some xHCI implementations may support 64-bit address pointers.  Registers

 * with 64-bit address pointers should be written to with dword accesses by

 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.

 * xHCI implementations that do not support 64-bit address pointers will ignore

 * the high dword, and write order is irrelevant.

 */

static inline void xhci_write_64(struct xhci_hcd *xhci,

				 const u64 val, __le64 __iomem *regs)

{

	__u32 __iomem *ptr = (__u32 __iomem *) regs;

	u32 val_lo = lower_32_bits(val);

	u32 val_hi = upper_32_bits(val);



	writel(val_lo, ptr);

	writel(val_hi, ptr + 1);

}



static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)

{

	return xhci->quirks & XHCI_LINK_TRB_QUIRK;

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