Commit 7db906b7 authored by Huang Shijie's avatar Huang Shijie Committed by Brian Norris
Browse files

mtd: nand: rename the cellinfo to bits_per_cell 



The @cellinfo fields contains unused information, such as write caching,
internal chip numbering, etc. But we only use it to check the SLC or MLC.

This patch tries to make it more clear and simple, renames the @cellinfo
to @bits_per_cell.

In order to avoiding the bisect issue, this patch also does the following
changes:
  (0) add a macro NAND_CI_CELLTYPE_SHIFT to avoid the hardcode.

  (1) add a helper to parse out the cell type : nand_get_bits_per_cell()

  (2) parse out the cell type for extended-ID chips and the full-id nand chips.

Signed-off-by: default avatarHuang Shijie <b32955@freescale.com>
Signed-off-by: default avatarBrian Norris <computersforpeace@gmail.com>
parent 1d0ed69d

drivers/mtd/nand/nand_base.c

+12 −2
Original line number Diff line number Diff line
@@ -3082,6 +3082,16 @@ static int nand_id_len(u8 *id_data, int arrlen) 
	return arrlen;

}



/* Extract the bits of per cell from the 3rd byte of the extended ID */

static int nand_get_bits_per_cell(u8 cellinfo)

{

	int bits;



	bits = cellinfo & NAND_CI_CELLTYPE_MSK;

	bits >>= NAND_CI_CELLTYPE_SHIFT;

	return bits + 1;

}



/*

 * Many new NAND share similar device ID codes, which represent the size of the

 * chip. The rest of the parameters must be decoded according to generic or
@@ -3092,7 +3102,7 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, 
{

	int extid, id_len;

	/* The 3rd id byte holds MLC / multichip data */

	chip->cellinfo = id_data[2];

	chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);

	/* The 4th id byte is the important one */

	extid = id_data[3];
@@ -3292,7 +3302,7 @@ static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip, 
		mtd->erasesize = type->erasesize;

		mtd->oobsize = type->oobsize;



		chip->cellinfo = id_data[2];

		chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);

		chip->chipsize = (uint64_t)type->chipsize << 20;

		chip->options |= type->options;

		chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);

include/linux/mtd/nand.h

+4 −3
Original line number Diff line number Diff line
@@ -198,6 +198,7 @@ typedef enum { 
/* Cell info constants */

#define NAND_CI_CHIPNR_MSK	0x03

#define NAND_CI_CELLTYPE_MSK	0x0C

#define NAND_CI_CELLTYPE_SHIFT	2



/* Keep gcc happy */

struct nand_chip;
@@ -477,7 +478,7 @@ struct nand_buffers { 
 * @badblockbits:	[INTERN] minimum number of set bits in a good block's

 *			bad block marker position; i.e., BBM == 11110111b is

 *			not bad when badblockbits == 7

 * @cellinfo:		[INTERN] MLC/multichip data from chip ident

 * @bits_per_cell:	[INTERN] number of bits per cell. i.e., 1 means SLC.

 * @ecc_strength_ds:	[INTERN] ECC correctability from the datasheet.

 *			Minimum amount of bit errors per @ecc_step_ds guaranteed

 *			to be correctable. If unknown, set to zero.
@@ -558,7 +559,7 @@ struct nand_chip { 
	int pagebuf;

	unsigned int pagebuf_bitflips;

	int subpagesize;

	uint8_t cellinfo;

	uint8_t bits_per_cell;

	uint16_t ecc_strength_ds;

	uint16_t ecc_step_ds;

	int badblockpos;
@@ -802,6 +803,6 @@ static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) 
 */

static inline bool nand_is_slc(struct nand_chip *chip)

{

	return !(chip->cellinfo & NAND_CI_CELLTYPE_MSK);

	return chip->bits_per_cell == 1;

}

#endif /* __LINUX_MTD_NAND_H */

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