Commit 7da3ad6c authored by Muhammad Sammar's avatar Muhammad Sammar Committed by Saeed Mahameed
Browse files

net/mlx5: Add misc4 to mlx5_ifc_fte_match_param_bits 



Add misc4 match params to enable matching on prog_sample_fields.

Signed-off-by: default avatarMuhammad Sammar <muhammads@nvidia.com>
Reviewed-by: default avatarAlex Vesker <valex@nvidia.com>
Reviewed-by: default avatarMark Bloch <mbloch@nvidia.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@nvidia.com>
parent 699d531f

drivers/net/ethernet/mellanox/mlx5/core/fs_core.h

+1 −1
Original line number Diff line number Diff line
@@ -194,7 +194,7 @@ struct mlx5_ft_underlay_qp { 
	u32 qpn;

};



#define MLX5_FTE_MATCH_PARAM_RESERVED	reserved_at_a00

#define MLX5_FTE_MATCH_PARAM_RESERVED	reserved_at_c00

/* Calculate the fte_match_param length and without the reserved length.

 * Make sure the reserved field is the last.

 */

include/linux/mlx5/device.h

+1 −0
Original line number Diff line number Diff line
@@ -1076,6 +1076,7 @@ enum { 
	MLX5_MATCH_INNER_HEADERS	= 1 << 2,

	MLX5_MATCH_MISC_PARAMETERS_2	= 1 << 3,

	MLX5_MATCH_MISC_PARAMETERS_3	= 1 << 4,

	MLX5_MATCH_MISC_PARAMETERS_4	= 1 << 5,

};



enum {

include/linux/mlx5/mlx5_ifc.h

+24 −1
Original line number Diff line number Diff line
@@ -623,6 +623,26 @@ struct mlx5_ifc_fte_match_set_misc3_bits { 
	u8         reserved_at_140[0xc0];

};



struct mlx5_ifc_fte_match_set_misc4_bits {

	u8         prog_sample_field_value_0[0x20];



	u8         prog_sample_field_id_0[0x20];



	u8         prog_sample_field_value_1[0x20];



	u8         prog_sample_field_id_1[0x20];



	u8         prog_sample_field_value_2[0x20];



	u8         prog_sample_field_id_2[0x20];



	u8         prog_sample_field_value_3[0x20];



	u8         prog_sample_field_id_3[0x20];



	u8         reserved_at_100[0x100];

};



struct mlx5_ifc_cmd_pas_bits {

	u8         pa_h[0x20];
@@ -1669,7 +1689,9 @@ struct mlx5_ifc_fte_match_param_bits { 


	struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;



	u8         reserved_at_a00[0x600];

	struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;



	u8         reserved_at_c00[0x400];

};



enum {
@@ -5462,6 +5484,7 @@ enum { 
	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,

	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,

	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,

	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,

};



struct mlx5_ifc_query_flow_group_out_bits {

include/uapi/rdma/mlx5_user_ioctl_cmds.h

+1 −1
Original line number Diff line number Diff line
@@ -232,7 +232,7 @@ enum mlx5_ib_device_query_context_attrs { 
	MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX = (1U << UVERBS_ID_NS_SHIFT),

};



#define MLX5_IB_DW_MATCH_PARAM 0x80

#define MLX5_IB_DW_MATCH_PARAM 0x90



struct mlx5_ib_match_params {

	__u32	match_params[MLX5_IB_DW_MATCH_PARAM];

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