Merge tag 'phy-for-4.20' of...

     "brcm,iproc-nsp-sata-phy"

     "brcm,phy-sata3"

     "brcm,iproc-sr-sata-phy"

     "brcm,bcm63138-sata-phy"

- address-cells: should be 1

- size-cells: should be 0

- reg: register ranges for the PHY PCB interface

Cadence MHDP DisplayPort SD0801 PHY binding

===========================================

This binding describes the Cadence SD0801 PHY hardware included with

the Cadence MHDP DisplayPort controller.

-------------------------------------------------------------------------------

Required properties (controller (parent) node):

- compatible	: Should be "cdns,dp-phy"

- reg		: Defines the following sets of registers in the parent

		  mhdp device:

			- Offset of the DPTX PHY configuration registers

			- Offset of the SD0801 PHY configuration registers

- #phy-cells	: from the generic PHY bindings, must be 0.

Optional properties:

- num_lanes	: Number of DisplayPort lanes to use (1, 2 or 4)

- max_bit_rate	: Maximum DisplayPort link bit rate to use, in Mbps (2160,

		  2430, 2700, 3240, 4320, 5400 or 8100)

-------------------------------------------------------------------------------

Example:

	dp_phy: phy@f0fb030a00 {

		compatible = "cdns,dp-phy";

		reg = <0xf0 0xfb030a00 0x0 0x00000040>,

		      <0xf0 0xfb500000 0x0 0x00100000>;

		num_lanes = <4>;

		max_bit_rate = <8100>;

		#phy-cells = <0>;

	};

ROCKCHIP HDMI PHY WITH INNO IP BLOCK

Required properties:

 - compatible : should be one of the listed compatibles:

	* "rockchip,rk3228-hdmi-phy",

	* "rockchip,rk3328-hdmi-phy";

 - reg : Address and length of the hdmi phy control register set

 - clocks : phandle + clock specifier for the phy clocks

 - clock-names : string, clock name, must contain "sysclk" for system

	  control and register configuration, "refoclk" for crystal-

	  oscillator reference PLL clock input and "refpclk" for pclk-

	  based refeference PLL clock input.

 - #clock-cells: should be 0.

 - clock-output-names : shall be the name for the output clock.

 - interrupts : phandle + interrupt specified for the hdmiphy interrupt

 - #phy-cells : must be 0. See ./phy-bindings.txt for details.

Optional properties for rk3328-hdmi-phy:

 - nvmem-cells = phandle + nvmem specifier for the cpu-version efuse

 - nvmem-cell-names : "cpu-version" to read the chip version, required

	  for adjustment to some frequency settings

Example:

	hdmi_phy: hdmi-phy@12030000 {

		compatible = "rockchip,rk3228-hdmi-phy";

		reg = <0x12030000 0x10000>;

		#phy-cells = <0>;

		clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;

		clock-names = "sysclk", "refoclk", "refpclk";

		#clock-cells = <0>;

		clock-output-names = "hdmi_phy";

		status = "disabled";

	};

Then the PHY can be used in other nodes such as:

	hdmi: hdmi@200a0000 {

		compatible = "rockchip,rk3228-dw-hdmi";

		...

		phys = <&hdmi_phy>;

		phy-names = "hdmi";

		...

	};

	       "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,

	       "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996,

	       "qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845,

	       "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845.

	       "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845,

	       "qcom,sdm845-qmp-ufs-phy" for UFS QMP phy on sdm845.

- reg:

  - index 0: address and length of register set for PHY's common

             serdes block.

  - index 1: address and length of the DP_COM control block (for

             "qcom,sdm845-qmp-usb3-phy" only).

- reg-names:

  - For "qcom,sdm845-qmp-usb3-phy":

     - index 0: address and length of register set for PHY's common serdes

       block.

     - named register "dp_com" (using reg-names): address and length of the

       DP_COM control block.

    - Should be: "reg-base", "dp_com"

  - For all others:

     - offset and length of register set for PHY's common serdes block.

    - The reg-names property shouldn't be defined.

 - #clock-cells: must be 1

    - Phy pll outputs a bunch of clocks for Tx, Rx and Pipe

		"aux" for phy aux clock,

		"ref" for 19.2 MHz ref clk,

		"com_aux" for phy common block aux clock,

		"ref_aux" for phy reference aux clock,

		For "qcom,msm8996-qmp-pcie-phy" must contain:

			"aux", "cfg_ahb", "ref".

		For "qcom,msm8996-qmp-usb3-phy" must contain:

* Renesas R-Car generation 3 USB 2.0 PHY

This file provides information on what the device node for the R-Car generation

3 USB 2.0 PHY contains.

3 and RZ/G2 USB 2.0 PHY contain.

Required properties:

- compatible: "renesas,usb2-phy-r8a7795" if the device is a part of an R8A7795

- compatible: "renesas,usb2-phy-r8a774a1" if the device is a part of an R8A774A1

	      SoC.

	      "renesas,usb2-phy-r8a7795" if the device is a part of an R8A7795

	      SoC.

	      "renesas,usb2-phy-r8a7796" if the device is a part of an R8A7796

	      SoC.

	      R8A77990 SoC.

	      "renesas,usb2-phy-r8a77995" if the device is a part of an

	      R8A77995 SoC.

	      "renesas,rcar-gen3-usb2-phy" for a generic R-Car Gen3 compatible device.

	      "renesas,rcar-gen3-usb2-phy" for a generic R-Car Gen3 or RZ/G2

	      compatible device.

	      When compatible with the generic version, nodes must list the

	      SoC-specific version corresponding to the platform first

- interrupts: interrupt specifier for the PHY.

- vbus-supply: Phandle to a regulator that provides power to the VBUS. This

	       regulator will be managed during the PHY power on/off sequence.

- renesas,no-otg-pins: boolean, specify when a board does not provide proper

		       otg pins.

Example (R-Car H3):