Commit 7d8d968d authored by rex zhu's avatar rex zhu Committed by Alex Deucher
Browse files

drm/amd/pp: Switch the tolerable latency for display 



Select the lowest MCLK frequency that is within
the tolerable latency defined in DISPALY

Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6eb9d603

drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

+1 −1
Original line number Diff line number Diff line
@@ -3217,7 +3217,7 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, 
		/* Find the lowest MCLK frequency that is within

		 * the tolerable latency defined in DAL

		 */

		latency = 0;

		latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;

		for (i = 0; i < data->mclk_latency_table.count; i++) {

			if ((data->mclk_latency_table.entries[i].latency <= latency) &&

				(data->mclk_latency_table.entries[i].frequency >=

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