Commit 7d754f97 authored by Ping-Ke Shih's avatar Ping-Ke Shih Committed by Kalle Valo
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rtw88: 8723d: implement flush queue



Flush queue is used to check if queue is empty, before doing something
else. Since 8723D uses different registers and page number of
availabl/reserved occupy 8 bits instead of 16 bits, so use a 'wsize' field
to discriminate which rtw_read{8,16} is adopted.

Signed-off-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Signed-off-by: default avatarYan-Hsuan Chuang <yhchuang@realtek.com>
Signed-off-by: default avatarKalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/20200512102621.5148-6-yhchuang@realtek.com
parent 05202746
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+11 −18
Original line number Diff line number Diff line
@@ -919,31 +919,24 @@ static u32 get_priority_queues(struct rtw_dev *rtwdev, u32 queues)
static void __rtw_mac_flush_prio_queue(struct rtw_dev *rtwdev,
				       u32 prio_queue, bool drop)
{
	u32 addr;
	struct rtw_chip_info *chip = rtwdev->chip;
	const struct rtw_prioq_addr *addr;
	bool wsize;
	u16 avail_page, rsvd_page;
	int i;

	switch (prio_queue) {
	case RTW_DMA_MAPPING_EXTRA:
		addr = REG_FIFOPAGE_INFO_4;
		break;
	case RTW_DMA_MAPPING_LOW:
		addr = REG_FIFOPAGE_INFO_2;
		break;
	case RTW_DMA_MAPPING_NORMAL:
		addr = REG_FIFOPAGE_INFO_3;
		break;
	case RTW_DMA_MAPPING_HIGH:
		addr = REG_FIFOPAGE_INFO_1;
		break;
	default:
	if (prio_queue >= RTW_DMA_MAPPING_MAX)
		return;
	}

	addr = &chip->prioq_addrs->prio[prio_queue];
	wsize = chip->prioq_addrs->wsize;

	/* check if all of the reserved pages are available for 100 msecs */
	for (i = 0; i < 5; i++) {
		rsvd_page = rtw_read16(rtwdev, addr);
		avail_page = rtw_read16(rtwdev, addr + 2);
		rsvd_page = wsize ? rtw_read16(rtwdev, addr->rsvd) :
				     rtw_read8(rtwdev, addr->rsvd);
		avail_page = wsize ? rtw_read16(rtwdev, addr->avail) :
				      rtw_read8(rtwdev, addr->avail);
		if (rsvd_page == avail_page)
			return;

+11 −0
Original line number Diff line number Diff line
@@ -945,6 +945,16 @@ struct rtw_rqpn {
	enum rtw_dma_mapping dma_map_hi;
};

struct rtw_prioq_addr {
	u32 rsvd;
	u32 avail;
};

struct rtw_prioq_addrs {
	struct rtw_prioq_addr prio[RTW_DMA_MAPPING_MAX];
	bool wsize;
};

struct rtw_page_table {
	u16 hq_num;
	u16 nq_num;
@@ -1101,6 +1111,7 @@ struct rtw_chip_info {
	const struct rtw_pwr_seq_cmd **pwr_on_seq;
	const struct rtw_pwr_seq_cmd **pwr_off_seq;
	const struct rtw_rqpn *rqpn_table;
	const struct rtw_prioq_addrs *prioq_addrs;
	const struct rtw_page_table *page_table;
	const struct rtw_intf_phy_para_table *intf_table;

+17 −0
Original line number Diff line number Diff line
@@ -2237,6 +2237,22 @@ static const struct rtw_rqpn rqpn_table_8723d[] = {
	 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
};

static const struct rtw_prioq_addrs prioq_addrs_8723d = {
	.prio[RTW_DMA_MAPPING_EXTRA] = {
		.rsvd = REG_RQPN_NPQ + 2, .avail = REG_RQPN_NPQ + 3,
	},
	.prio[RTW_DMA_MAPPING_LOW] = {
		.rsvd = REG_RQPN + 1, .avail = REG_FIFOPAGE_CTRL_2 + 1,
	},
	.prio[RTW_DMA_MAPPING_NORMAL] = {
		.rsvd = REG_RQPN_NPQ, .avail = REG_RQPN_NPQ + 1,
	},
	.prio[RTW_DMA_MAPPING_HIGH] = {
		.rsvd = REG_RQPN, .avail = REG_FIFOPAGE_CTRL_2,
	},
	.wsize = false,
};

static const struct rtw_intf_phy_para pcie_gen1_param_8723d[] = {
	{0x0008, 0x4a22,
	 RTW_IP_SEL_PHY,
@@ -2370,6 +2386,7 @@ struct rtw_chip_info rtw8723d_hw_spec = {
	.pwr_off_seq = card_disable_flow_8723d,
	.page_table = page_table_8723d,
	.rqpn_table = rqpn_table_8723d,
	.prioq_addrs = &prioq_addrs_8723d,
	.intf_table = &phy_para_table_8723d,
	.dig = rtw8723d_dig,
	.dig_cck = rtw8723d_dig_cck,
+17 −0
Original line number Diff line number Diff line
@@ -2083,6 +2083,22 @@ static const struct rtw_rqpn rqpn_table_8822b[] = {
	 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
};

static struct rtw_prioq_addrs prioq_addrs_8822b = {
	.prio[RTW_DMA_MAPPING_EXTRA] = {
		.rsvd = REG_FIFOPAGE_INFO_4, .avail = REG_FIFOPAGE_INFO_4 + 2,
	},
	.prio[RTW_DMA_MAPPING_LOW] = {
		.rsvd = REG_FIFOPAGE_INFO_2, .avail = REG_FIFOPAGE_INFO_2 + 2,
	},
	.prio[RTW_DMA_MAPPING_NORMAL] = {
		.rsvd = REG_FIFOPAGE_INFO_3, .avail = REG_FIFOPAGE_INFO_3 + 2,
	},
	.prio[RTW_DMA_MAPPING_HIGH] = {
		.rsvd = REG_FIFOPAGE_INFO_1, .avail = REG_FIFOPAGE_INFO_1 + 2,
	},
	.wsize = true,
};

static struct rtw_chip_ops rtw8822b_ops = {
	.phy_set_param		= rtw8822b_phy_set_param,
	.read_efuse		= rtw8822b_read_efuse,
@@ -2433,6 +2449,7 @@ struct rtw_chip_info rtw8822b_hw_spec = {
	.pwr_off_seq = card_disable_flow_8822b,
	.page_table = page_table_8822b,
	.rqpn_table = rqpn_table_8822b,
	.prioq_addrs = &prioq_addrs_8822b,
	.intf_table = &phy_para_table_8822b,
	.dig = rtw8822b_dig,
	.dig_cck = NULL,
+17 −0
Original line number Diff line number Diff line
@@ -3933,6 +3933,22 @@ static const struct rtw_rqpn rqpn_table_8822c[] = {
	 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
};

static struct rtw_prioq_addrs prioq_addrs_8822c = {
	.prio[RTW_DMA_MAPPING_EXTRA] = {
		.rsvd = REG_FIFOPAGE_INFO_4, .avail = REG_FIFOPAGE_INFO_4 + 2,
	},
	.prio[RTW_DMA_MAPPING_LOW] = {
		.rsvd = REG_FIFOPAGE_INFO_2, .avail = REG_FIFOPAGE_INFO_2 + 2,
	},
	.prio[RTW_DMA_MAPPING_NORMAL] = {
		.rsvd = REG_FIFOPAGE_INFO_3, .avail = REG_FIFOPAGE_INFO_3 + 2,
	},
	.prio[RTW_DMA_MAPPING_HIGH] = {
		.rsvd = REG_FIFOPAGE_INFO_1, .avail = REG_FIFOPAGE_INFO_1 + 2,
	},
	.wsize = true,
};

static struct rtw_chip_ops rtw8822c_ops = {
	.phy_set_param		= rtw8822c_phy_set_param,
	.read_efuse		= rtw8822c_read_efuse,
@@ -4295,6 +4311,7 @@ struct rtw_chip_info rtw8822c_hw_spec = {
	.pwr_off_seq = card_disable_flow_8822c,
	.page_table = page_table_8822c,
	.rqpn_table = rqpn_table_8822c,
	.prioq_addrs = &prioq_addrs_8822c,
	.intf_table = &phy_para_table_8822c,
	.dig = rtw8822c_dig,
	.dig_cck = NULL,