Commit 7d4c75d9 authored by Mika Kuoppala's avatar Mika Kuoppala Committed by Chris Wilson
Browse files

drm/i915: Prepare for larger CSB status FIFO size 



Make csb entry count variable in preparation for larger
CSB status FIFO size found on gen11+ hardware.

v2: adapt to hwsp access only (Chris)
    non continuous mmio (Daniele)
v3: entries (Chris), fix macro for checkpatch
v4: num_entries (Chris)
v5: consistency on num_entries

Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190405204657.12887-1-chris@chris-wilson.co.uk
parent 917dc6b5

drivers/gpu/drm/i915/intel_engine_cs.c

+11 −18
Original line number Diff line number Diff line
@@ -1405,40 +1405,33 @@ static void intel_engine_print_registers(const struct intel_engine_cs *engine, 
	if (HAS_EXECLISTS(dev_priv)) {

		const u32 *hws =

			&engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];

		const u8 num_entries = execlists->csb_size;

		unsigned int idx;

		u8 read, write;



		drm_printf(m, "\tExeclist status: 0x%08x %08x\n",

		drm_printf(m, "\tExeclist status: 0x%08x %08x, entries %u\n",

			   ENGINE_READ(engine, RING_EXECLIST_STATUS_LO),

			   ENGINE_READ(engine, RING_EXECLIST_STATUS_HI));

			   ENGINE_READ(engine, RING_EXECLIST_STATUS_HI),

			   num_entries);



		read = execlists->csb_head;

		write = READ_ONCE(*execlists->csb_write);



		drm_printf(m, "\tExeclist CSB read %d, write %d [mmio:%d], tasklet queued? %s (%s)\n",

		drm_printf(m, "\tExeclist CSB read %d, write %d, tasklet queued? %s (%s)\n",

			   read, write,

			   GEN8_CSB_WRITE_PTR(ENGINE_READ(engine, RING_CONTEXT_STATUS_PTR)),

			   yesno(test_bit(TASKLET_STATE_SCHED,

					  &engine->execlists.tasklet.state)),

			   enableddisabled(!atomic_read(&engine->execlists.tasklet.count)));

		if (read >= GEN8_CSB_ENTRIES)

		if (read >= num_entries)

			read = 0;

		if (write >= GEN8_CSB_ENTRIES)

		if (write >= num_entries)

			write = 0;

		if (read > write)

			write += GEN8_CSB_ENTRIES;

			write += num_entries;

		while (read < write) {

			idx = ++read % GEN8_CSB_ENTRIES;

			drm_printf(m, "\tExeclist CSB[%d]: 0x%08x [mmio:0x%08x], context: %d [mmio:%d]\n",

				   idx,

				   hws[idx * 2],

				   ENGINE_READ_IDX(engine,

						   RING_CONTEXT_STATUS_BUF_LO,

						   idx),

				   hws[idx * 2 + 1],

				   ENGINE_READ_IDX(engine,

						   RING_CONTEXT_STATUS_BUF_HI,

						   idx));

			idx = ++read % num_entries;

			drm_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n",

				   idx, hws[idx * 2], hws[idx * 2 + 1]);

		}



		rcu_read_lock();

drivers/gpu/drm/i915/intel_engine_types.h

+5 −0
Original line number Diff line number Diff line
@@ -246,6 +246,11 @@ struct intel_engine_execlists { 
	 */

	u32 preempt_complete_status;



	/**

	 * @csb_size: context status buffer FIFO size

	 */

	u8 csb_size;



	/**

	 * @csb_head: context status buffer head

	 */

drivers/gpu/drm/i915/intel_lrc.c

+5 −2
Original line number Diff line number Diff line
@@ -895,7 +895,7 @@ invalidate_csb_entries(const u32 *first, const u32 *last) 


static void reset_csb_pointers(struct intel_engine_execlists *execlists)

{

	const unsigned int reset_value = GEN8_CSB_ENTRIES - 1;

	const unsigned int reset_value = execlists->csb_size - 1;



	/*

	 * After a reset, the HW starts writing into CSB entry [0]. We
@@ -994,6 +994,7 @@ static void process_csb(struct intel_engine_cs *engine) 
	struct intel_engine_execlists * const execlists = &engine->execlists;

	struct execlist_port *port = execlists->port;

	const u32 * const buf = execlists->csb_status;

	const u8 num_entries = execlists->csb_size;

	u8 head, tail;



	lockdep_assert_held(&engine->timeline.lock);
@@ -1029,7 +1030,7 @@ static void process_csb(struct intel_engine_cs *engine) 
		unsigned int status;

		unsigned int count;



		if (++head == GEN8_CSB_ENTRIES)

		if (++head == num_entries)

			head = 0;



		/*
@@ -2476,6 +2477,8 @@ static int logical_ring_init(struct intel_engine_cs *engine) 
	execlists->csb_write =

		&engine->status_page.addr[intel_hws_csb_write_index(i915)];



	execlists->csb_size = GEN8_CSB_ENTRIES;



	reset_csb_pointers(execlists);



	return 0;

drivers/gpu/drm/i915/intel_lrc.h

+6 −7
Original line number Diff line number Diff line
@@ -36,12 +36,10 @@ 
#define	  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT	(1 << 0)

#define   CTX_CTRL_RS_CTX_ENABLE		(1 << 1)

#define	  CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT	(1 << 2)

#define RING_CONTEXT_STATUS_BUF_BASE(base)	_MMIO((base) + 0x370)

#define RING_CONTEXT_STATUS_BUF_LO(base, i)	_MMIO((base) + 0x370 + (i) * 8)

#define RING_CONTEXT_STATUS_BUF_HI(base, i)	_MMIO((base) + 0x370 + (i) * 8 + 4)

#define RING_CONTEXT_STATUS_PTR(base)		_MMIO((base) + 0x3a0)

#define RING_EXECLIST_SQ_CONTENTS(base)		_MMIO((base) + 0x510)

#define RING_EXECLIST_CONTROL(base)		_MMIO((base) + 0x550)



#define	  EL_CTRL_LOAD				(1 << 0)



/* The docs specify that the write pointer wraps around after 5h, "After status
@@ -55,10 +53,11 @@ 
#define GEN8_CSB_PTR_MASK 0x7

#define GEN8_CSB_READ_PTR_MASK (GEN8_CSB_PTR_MASK << 8)

#define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0)

#define GEN8_CSB_WRITE_PTR(csb_status) \

	(((csb_status) & GEN8_CSB_WRITE_PTR_MASK) >> 0)

#define GEN8_CSB_READ_PTR(csb_status) \

	(((csb_status) & GEN8_CSB_READ_PTR_MASK) >> 8)



#define GEN11_CSB_ENTRIES 12

#define GEN11_CSB_PTR_MASK 0xf

#define GEN11_CSB_READ_PTR_MASK (GEN11_CSB_PTR_MASK << 8)

#define GEN11_CSB_WRITE_PTR_MASK (GEN11_CSB_PTR_MASK << 0)



enum {

	INTEL_CONTEXT_SCHEDULE_IN = 0,

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