Commit 7d49efe2 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-stable' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64 

Pull ARM64 fixes from Catalin Marinas:
 - Page table fixes (PROT_NONE, shareability attribute, TLB
   invalidation)
 - Secondary CPUs entry endianness fix
 - Make NR_CPUS default to 8

* tag 'arm64-stable' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64:
  arm64: mm: Fix PMD_SECT_PROT_NONE definition
  arm64: Fix memory shareability attribute for ioremap_wc/cache
  arm64: kernel: add code to set cpu boot mode to secondary_entry shim
  arm64: make default NR_CPUS 8
  arm64: ensure completion of TLB invalidatation
parents 374b1057 db4ed53c

arch/arm64/Kconfig

+1 −2
Original line number Diff line number Diff line
@@ -159,8 +159,7 @@ config NR_CPUS 
	range 2 32

	depends on SMP

	# These have to remain sorted largest to smallest

	default "8" if ARCH_XGENE

	default "4"

	default "8"



config HOTPLUG_CPU

	bool "Support for hot-pluggable CPUs"

arch/arm64/include/asm/io.h

+1 −1
Original line number Diff line number Diff line
@@ -229,7 +229,7 @@ extern void __iomem *__ioremap(phys_addr_t phys_addr, size_t size, pgprot_t prot 
extern void __iounmap(volatile void __iomem *addr);

extern void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size);



#define PROT_DEFAULT		(PTE_TYPE_PAGE | PTE_AF | PTE_DIRTY)

#define PROT_DEFAULT		(pgprot_default | PTE_DIRTY)

#define PROT_DEVICE_nGnRE	(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRE))

#define PROT_NORMAL_NC		(PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL_NC))

#define PROT_NORMAL		(PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL))

arch/arm64/include/asm/pgtable-hwdef.h

+1 −1
Original line number Diff line number Diff line
@@ -43,7 +43,7 @@ 
 * Section

 */

#define PMD_SECT_VALID		(_AT(pmdval_t, 1) << 0)

#define PMD_SECT_PROT_NONE	(_AT(pmdval_t, 1) << 2)

#define PMD_SECT_PROT_NONE	(_AT(pmdval_t, 1) << 58)

#define PMD_SECT_USER		(_AT(pmdval_t, 1) << 6)		/* AP[1] */

#define PMD_SECT_RDONLY		(_AT(pmdval_t, 1) << 7)		/* AP[2] */

#define PMD_SECT_S		(_AT(pmdval_t, 3) << 8)

arch/arm64/kernel/head.S

+2 −1
Original line number Diff line number Diff line
@@ -282,8 +282,9 @@ ENDPROC(secondary_holding_pen) 
	 * be used where CPUs are brought online dynamically by the kernel.

	 */

ENTRY(secondary_entry)

	bl	__calc_phys_offset		// x2=phys offset

	bl	el2_setup			// Drop to EL1

	bl	__calc_phys_offset		// x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET

	bl	set_cpu_boot_mode_flag

	b	secondary_startup

ENDPROC(secondary_entry)

arch/arm64/mm/proc.S

+1 −1
Original line number Diff line number Diff line
@@ -111,12 +111,12 @@ ENTRY(__cpu_setup) 
	bl	__flush_dcache_all

	mov	lr, x28

	ic	iallu				// I+BTB cache invalidate

	tlbi	vmalle1is			// invalidate I + D TLBs

	dsb	sy



	mov	x0, #3 << 20

	msr	cpacr_el1, x0			// Enable FP/ASIMD

	msr	mdscr_el1, xzr			// Reset mdscr_el1

	tlbi	vmalle1is			// invalidate I + D TLBs

	/*

	 * Memory region attributes for LPAE:

	 *

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