Commit 7d3ef43f authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'reset-for-4.9' of git://git.pengutronix.de/git/pza/linux into next/drivers 

Merge "Reset controller changes for v4.9" from Philipp Zabel:

- add reset controller driver Kconfig options,
  allow building drivers with COMPILE_TEST
- add reset controller driver for UniPhier SoCs
- add reset controller driver for STM32 MCUs
- simplify SoCFPGA reset controller driver a bit

* tag 'reset-for-4.9' of git://git.pengutronix.de/git/pza/linux:
  reset: hi6220: allow to compile test driver on other architectures
  reset: zynq: add driver Kconfig option
  reset: sunxi: add driver Kconfig option
  reset: stm32: add driver Kconfig option
  reset: socfpga: add driver Kconfig option
  reset: pistachio: add driver Kconfig option
  reset: meson: add driver Kconfig option
  reset: lpc18xx: add driver Kconfig option
  reset: berlin: add driver Kconfig option
  reset: ath79: add driver Kconfig option
  reset: ath79: add missing include
  reset: warn on invalid input to reset_control_reset/assert/deassert/status
  reset: uniphier: add reset controller driver for UniPhier SoCs
  ARM: dts: stm32f429: add missing #reset-cells of rcc
  drivers: reset: Add STM32 reset driver
  dt-bindings: Document the STM32 reset bindings
  dt-bindings: mfd: Add STM32F4 RCC numeric constants into DT include file
  reset: socfpga: no need to store modrst_offset
parents 2b97f10b cddb4800

Documentation/devicetree/bindings/clock/st,stm32-rcc.txt

+35 −7
Original line number Diff line number Diff line 
STMicroelectronics STM32 Reset and Clock Controller

===================================================



The RCC IP is both a reset and a clock controller. This documentation only

describes the clock part.

The RCC IP is both a reset and a clock controller.



Please also refer to clock-bindings.txt in this directory for common clock

controller binding usage.

Please refer to clock-bindings.txt for common clock controller binding usage.

Please also refer to reset.txt for common reset controller binding usage.



Required properties:

- compatible: Should be "st,stm32f42xx-rcc"

- reg: should be register base and length as documented in the

  datasheet

- #reset-cells: 1, see below

- #clock-cells: 2, device nodes should specify the clock in their "clocks"

  property, containing a phandle to the clock device node, an index selecting

  between gated clocks and other clocks and an index specifying the clock to
@@ -19,6 +19,7 @@ Required properties: 
Example:



	rcc: rcc@40023800 {

		#reset-cells = <1>;

		#clock-cells = <2>

		compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";

		reg = <0x40023800 0x400>;
@@ -35,16 +36,23 @@ from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30). 
It is calculated as: index = register_offset / 4 * 32 + bit_offset.

Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31).



To simplify the usage and to share bit definition with the reset and clock

drivers of the RCC IP, macros are available to generate the index in

human-readble format.



For STM32F4 series, the macro are available here:

 - include/dt-bindings/mfd/stm32f4-rcc.h



Example:



	/* Gated clock, AHB1 bit 0 (GPIOA) */

	... {

		clocks = <&rcc 0 0>

		clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>

	};



	/* Gated clock, AHB2 bit 4 (CRYP) */

	... {

		clocks = <&rcc 0 36>

		clocks = <&rcc 0 STM32F4_AHB2_CLOCK(CRYP)>

	};



Specifying other clocks
@@ -61,5 +69,25 @@ Example: 


	/* Misc clock, FCLK */

	... {

		clocks = <&rcc 1 1>

		clocks = <&rcc 1 STM32F4_APB1_CLOCK(TIM2)>

	};





Specifying softreset control of devices

=======================================



Device nodes should specify the reset channel required in their "resets"

property, containing a phandle to the reset device node and an index specifying

which channel to use.

The index is the bit number within the RCC registers bank, starting from RCC

base address.

It is calculated as: index = register_offset / 4 * 32 + bit_offset.

Where bit_offset is the bit offset within the register.

For example, for CRC reset:

  crc = AHB1RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x10 / 4 * 32 + 12 = 140



example:



	timer2 {

		resets	= <&rcc STM32F4_APB1_RESET(TIM2)>;

	};

Documentation/devicetree/bindings/reset/st,stm32-rcc.txt

0 → 100644
+6 −0
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STMicroelectronics STM32 Peripheral Reset Controller

====================================================



The RCC IP is both a reset and a clock controller.



Please see Documentation/devicetree/bindings/clock/st,stm32-rcc.txt

Documentation/devicetree/bindings/reset/uniphier-reset.txt

0 → 100644
+93 −0
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UniPhier reset controller





System reset

------------



Required properties:

- compatible: should be one of the following:

    "socionext,uniphier-sld3-reset" - for PH1-sLD3 SoC.

    "socionext,uniphier-ld4-reset"  - for PH1-LD4 SoC.

    "socionext,uniphier-pro4-reset" - for PH1-Pro4 SoC.

    "socionext,uniphier-sld8-reset" - for PH1-sLD8 SoC.

    "socionext,uniphier-pro5-reset" - for PH1-Pro5 SoC.

    "socionext,uniphier-pxs2-reset" - for ProXstream2/PH1-LD6b SoC.

    "socionext,uniphier-ld11-reset" - for PH1-LD11 SoC.

    "socionext,uniphier-ld20-reset" - for PH1-LD20 SoC.

- #reset-cells: should be 1.



Example:



	sysctrl@61840000 {

		compatible = "socionext,uniphier-ld20-sysctrl",

			     "simple-mfd", "syscon";

		reg = <0x61840000 0x4000>;



		reset {

			compatible = "socionext,uniphier-ld20-reset";

			#reset-cells = <1>;

		};



		other nodes ...

	};





Media I/O (MIO) reset

---------------------



Required properties:

- compatible: should be one of the following:

    "socionext,uniphier-sld3-mio-reset" - for PH1-sLD3 SoC.

    "socionext,uniphier-ld4-mio-reset"  - for PH1-LD4 SoC.

    "socionext,uniphier-pro4-mio-reset" - for PH1-Pro4 SoC.

    "socionext,uniphier-sld8-mio-reset" - for PH1-sLD8 SoC.

    "socionext,uniphier-pro5-mio-reset" - for PH1-Pro5 SoC.

    "socionext,uniphier-pxs2-mio-reset" - for ProXstream2/PH1-LD6b SoC.

    "socionext,uniphier-ld11-mio-reset" - for PH1-LD11 SoC.

    "socionext,uniphier-ld20-mio-reset" - for PH1-LD20 SoC.

- #reset-cells: should be 1.



Example:



	mioctrl@59810000 {

		compatible = "socionext,uniphier-ld20-mioctrl",

			     "simple-mfd", "syscon";

		reg = <0x59810000 0x800>;



		reset {

			compatible = "socionext,uniphier-ld20-mio-reset";

			#reset-cells = <1>;

		};



		other nodes ...

	};





Peripheral reset

----------------



Required properties:

- compatible: should be one of the following:

    "socionext,uniphier-ld4-peri-reset"  - for PH1-LD4 SoC.

    "socionext,uniphier-pro4-peri-reset" - for PH1-Pro4 SoC.

    "socionext,uniphier-sld8-peri-reset" - for PH1-sLD8 SoC.

    "socionext,uniphier-pro5-peri-reset" - for PH1-Pro5 SoC.

    "socionext,uniphier-pxs2-peri-reset" - for ProXstream2/PH1-LD6b SoC.

    "socionext,uniphier-ld11-peri-reset" - for PH1-LD11 SoC.

    "socionext,uniphier-ld20-peri-reset" - for PH1-LD20 SoC.

- #reset-cells: should be 1.



Example:



	perictrl@59820000 {

		compatible = "socionext,uniphier-ld20-perictrl",

			     "simple-mfd", "syscon";

		reg = <0x59820000 0x200>;



		reset {

			compatible = "socionext,uniphier-ld20-peri-reset";

			#reset-cells = <1>;

		};



		other nodes ...

	};

MAINTAINERS

+1 −0
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@@ -1840,6 +1840,7 @@ F: arch/arm64/boot/dts/socionext/ 
F:	drivers/bus/uniphier-system-bus.c

F:	drivers/i2c/busses/i2c-uniphier*

F:	drivers/pinctrl/uniphier/

F:	drivers/reset/reset-uniphier.c

F:	drivers/tty/serial/8250/8250_uniphier.c

N:	uniphier

arch/arm/boot/dts/stm32f429.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -326,6 +326,7 @@ 
		};



		rcc: rcc@40023810 {

			#reset-cells = <1>;

			#clock-cells = <2>;

			compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";

			reg = <0x40023800 0x400>;

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