Commit 7d304e1c authored by Sergio Paracuellos's avatar Sergio Paracuellos Committed by Greg Kroah-Hartman
Browse files

staging: mt7621-dts: simplify pcie phy bindings 



If each phy port doesn't have its own resources, then we don't need
child nodes. Handle it using #phy-cells to 1 for both phy's.

Signed-off-by: default avatarSergio Paracuellos <sergio.paracuellos@gmail.com>
Reviewed-by: default avatarNeilBrown <neil@brown.name>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent c27d975a

drivers/staging/mt7621-dts/mt7621.dtsi

+3 −20
Original line number Diff line number Diff line
@@ -491,7 +491,7 @@ 
		reset-names = "pcie", "pcie0", "pcie1", "pcie2";

		clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;

		clock-names = "pcie0", "pcie1", "pcie2";

		phys = <&pcie0_port>, <&pcie1_port>, <&pcie2_port>;

		phys = <&pcie0_phy 0>, <&pcie0_phy 1>, <&pcie1_phy 0>;

		phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";



		pcie@0,0 {
@@ -522,29 +522,12 @@ 
	pcie0_phy: pcie-phy@1e149000 {

		compatible = "mediatek,mt7621-pci-phy";

		reg = <0x1e149000 0x0700>;

		#address-cells = <1>;

		#size-cells = <0>;



		pcie0_port: pcie-phy@0 {

			reg = <0>;

			#phy-cells = <0>;

		};



		pcie1_port: pcie-phy@1 {

			reg = <1>;

			#phy-cells = <0>;

		};

		#phy-cells = <1>;

	};



	pcie1_phy: pcie-phy@1e14a000 {

		compatible = "mediatek,mt7621-pci-phy";

		reg = <0x1e14a000 0x0700>;

		#address-cells = <1>;

		#size-cells = <0>;



		pcie2_port: pcie-phy@0 {

			reg = <0>;

			#phy-cells = <0>;

		};

		#phy-cells = <1>;

	};

};

CRA Git | Maintained and supported by SUSTech CRA and CCSE