drm/i915: Apply some ocd for IMR vs. IER order during irq enable (7d1bd539) · Commits · 戴 / test

When disabling interrupts we do the writes in this order: IMR,IER,IIR,IIR. But when enabling interrupts we don't do use the mirrored order, and instead do IIR,IIR,IMR,IER. I like consistency unless there's a good reason against it, which I can't think of here, so change the enable order to IIR,IIR,IER,IMR. Signed-off-by:

Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:

Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by:

Daniel Vetter <daniel.vetter@ffwll.ch>

drivers/gpu/drm/i915/i915_irq.c

+4 −4

Original line number	Diff line number	Diff line
		@@ -126,16 +126,16 @@ static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */

		#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
		GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
		I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
		I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
		POSTING_READ(GEN8_##type##_IER(which)); \
		I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
		POSTING_READ(GEN8_##type##_IMR(which)); \
		} while (0)

		#define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
		GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
		I915_WRITE(type##IMR, (imr_val)); \
		I915_WRITE(type##IER, (ier_val)); \
		POSTING_READ(type##IER); \
		I915_WRITE(type##IMR, (imr_val)); \
		POSTING_READ(type##IMR); \
		} while (0)

		/* For display hotplug interrupt */

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