Commit 7cef39dd authored by Jean-Philippe Brucker's avatar Jean-Philippe Brucker Committed by Will Deacon
Browse files

iommu/io-pgtable-arm: Move some definitions to a header 



Extract some of the most generic TCR defines, so they can be reused by
the page table sharing code.

Signed-off-by: default avatarJean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: default avatarWill Deacon <will@kernel.org>
Link: https://lore.kernel.org/r/20200918101852.582559-6-jean-philippe@linaro.org


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 8122dec0

MAINTAINERS

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@@ -1506,8 +1506,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 
S:	Maintained

F:	Documentation/devicetree/bindings/iommu/arm,smmu*

F:	drivers/iommu/arm/

F:	drivers/iommu/io-pgtable-arm-v7s.c

F:	drivers/iommu/io-pgtable-arm.c

F:	drivers/iommu/io-pgtable-arm*









ARM SUB-ARCHITECTURES









L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
































drivers/iommu/io-pgtable-arm.c



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@@ -20,6 +20,8 @@

















#include <asm/barrier.h>



















#include "io-pgtable-arm.h"



















#define ARM_LPAE_MAX_ADDR_BITS		52









#define ARM_LPAE_S2_MAX_CONCAT_PAGES	16









#define ARM_LPAE_MAX_LEVELS		4








@@ -100,23 +102,6 @@







#define ARM_LPAE_PTE_MEMATTR_DEV	(((arm_lpae_iopte)0x1) << 2)



















/* Register bits */









#define ARM_LPAE_TCR_TG0_4K		0









#define ARM_LPAE_TCR_TG0_64K		1









#define ARM_LPAE_TCR_TG0_16K		2



















#define ARM_LPAE_TCR_TG1_16K		1









#define ARM_LPAE_TCR_TG1_4K		2









#define ARM_LPAE_TCR_TG1_64K		3



















#define ARM_LPAE_TCR_SH_NS		0









#define ARM_LPAE_TCR_SH_OS		2









#define ARM_LPAE_TCR_SH_IS		3



















#define ARM_LPAE_TCR_RGN_NC		0









#define ARM_LPAE_TCR_RGN_WBWA		1









#define ARM_LPAE_TCR_RGN_WT		2









#define ARM_LPAE_TCR_RGN_WB		3



















#define ARM_LPAE_VTCR_SL0_MASK		0x3



















#define ARM_LPAE_TCR_T0SZ_SHIFT		0








@@ -124,14 +109,6 @@







#define ARM_LPAE_VTCR_PS_SHIFT		16









#define ARM_LPAE_VTCR_PS_MASK		0x7



















#define ARM_LPAE_TCR_PS_32_BIT		0x0ULL









#define ARM_LPAE_TCR_PS_36_BIT		0x1ULL









#define ARM_LPAE_TCR_PS_40_BIT		0x2ULL









#define ARM_LPAE_TCR_PS_42_BIT		0x3ULL









#define ARM_LPAE_TCR_PS_44_BIT		0x4ULL









#define ARM_LPAE_TCR_PS_48_BIT		0x5ULL









#define ARM_LPAE_TCR_PS_52_BIT		0x6ULL



















#define ARM_LPAE_MAIR_ATTR_SHIFT(n)	((n) << 3)









#define ARM_LPAE_MAIR_ATTR_MASK		0xff









#define ARM_LPAE_MAIR_ATTR_DEVICE	0x04
































drivers/iommu/io-pgtable-arm.h
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/* SPDX-License-Identifier: GPL-2.0-only */









#ifndef IO_PGTABLE_ARM_H_









#define IO_PGTABLE_ARM_H_



















#define ARM_LPAE_TCR_TG0_4K		0









#define ARM_LPAE_TCR_TG0_64K		1









#define ARM_LPAE_TCR_TG0_16K		2



















#define ARM_LPAE_TCR_TG1_16K		1









#define ARM_LPAE_TCR_TG1_4K		2









#define ARM_LPAE_TCR_TG1_64K		3



















#define ARM_LPAE_TCR_SH_NS		0









#define ARM_LPAE_TCR_SH_OS		2









#define ARM_LPAE_TCR_SH_IS		3



















#define ARM_LPAE_TCR_RGN_NC		0









#define ARM_LPAE_TCR_RGN_WBWA		1









#define ARM_LPAE_TCR_RGN_WT		2









#define ARM_LPAE_TCR_RGN_WB		3



















#define ARM_LPAE_TCR_PS_32_BIT		0x0ULL









#define ARM_LPAE_TCR_PS_36_BIT		0x1ULL









#define ARM_LPAE_TCR_PS_40_BIT		0x2ULL









#define ARM_LPAE_TCR_PS_42_BIT		0x3ULL









#define ARM_LPAE_TCR_PS_44_BIT		0x4ULL









#define ARM_LPAE_TCR_PS_48_BIT		0x5ULL









#define ARM_LPAE_TCR_PS_52_BIT		0x6ULL



















#endif /* IO_PGTABLE_ARM_H_ */


























































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