Commit 7ce4d1f2 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Clear VLV_IIR after PIPESTAT 



On VLV/CHV VLV_IIR is not double double buffered, and it doesn't detect
edges from PIPESTAT & co. like it does on gen4. Instead it just
directly latches the level from PIPESTAT & co. That means we must clear
VLV_IIR after PIPESTAT & co. or else we'll get a spurious bit in VLV_IIR
every single time.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1460571598-24452-4-git-send-email-ville.syrjala@linux.intel.com


Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent 34c7b8a7

drivers/gpu/drm/i915/i915_irq.c

+21 −15
Original line number Diff line number Diff line
@@ -1789,12 +1789,6 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg) 
			I915_WRITE(GEN6_PMIIR, pm_iir);



		iir = I915_READ(VLV_IIR);

		if (iir) {

			/* Consume port before clearing IIR or we'll miss events */

			if (iir & I915_DISPLAY_PORT_INTERRUPT)

				i9xx_hpd_irq_handler(dev);

			I915_WRITE(VLV_IIR, iir);

		}



		if (gt_iir == 0 && pm_iir == 0 && iir == 0)

			goto out;
@@ -1805,9 +1799,20 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg) 
			snb_gt_irq_handler(dev, dev_priv, gt_iir);

		if (pm_iir)

			gen6_rps_irq_handler(dev_priv, pm_iir);



		if (iir & I915_DISPLAY_PORT_INTERRUPT)

			i9xx_hpd_irq_handler(dev);



		/* Call regardless, as some status bits might not be

		 * signalled in iir */

		valleyview_pipestat_irq_handler(dev, iir);



		/*

		 * VLV_IIR is single buffered, and reflects the level

		 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.

		 */

		if (iir)

			I915_WRITE(VLV_IIR, iir);

	}



out:
@@ -1840,21 +1845,22 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg) 


		I915_WRITE(GEN8_MASTER_IRQ, 0);



		/* Find, clear, then process each source of interrupt */

		gen8_gt_irq_handler(dev_priv, master_ctl);



		if (iir) {

			/* Consume port before clearing IIR or we'll miss events */

		if (iir & I915_DISPLAY_PORT_INTERRUPT)

			i9xx_hpd_irq_handler(dev);

			I915_WRITE(VLV_IIR, iir);

		}



		gen8_gt_irq_handler(dev_priv, master_ctl);



		/* Call regardless, as some status bits might not be

		 * signalled in iir */

		valleyview_pipestat_irq_handler(dev, iir);



		/*

		 * VLV_IIR is single buffered, and reflects the level

		 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.

		 */

		if (iir)

			I915_WRITE(VLV_IIR, iir);



		I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);

		POSTING_READ(GEN8_MASTER_IRQ);

	} while (0);

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