Commit 7cdccb4c authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/dsb: use intel_de_*() functions for register access 



The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().

Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().

No functional changes.

Generated using the following semantic patch:

@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)

@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)

@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)

@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)

@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)

Acked-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Acked-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/fc2a561318089b9c80111039b2623eb3ad40e6a6.1579871655.git.jani.nikula@intel.com
parent 9ce64616

drivers/gpu/drm/i915/display/intel_dsb.c

+13 −11
Original line number Diff line number Diff line
@@ -40,7 +40,7 @@ static inline bool is_dsb_busy(struct intel_dsb *dsb) 
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	enum pipe pipe = crtc->pipe;



	return DSB_STATUS & I915_READ(DSB_CTRL(pipe, dsb->id));

	return DSB_STATUS & intel_de_read(dev_priv, DSB_CTRL(pipe, dsb->id));

}



static inline bool intel_dsb_enable_engine(struct intel_dsb *dsb)
@@ -50,16 +50,16 @@ static inline bool intel_dsb_enable_engine(struct intel_dsb *dsb) 
	enum pipe pipe = crtc->pipe;

	u32 dsb_ctrl;



	dsb_ctrl = I915_READ(DSB_CTRL(pipe, dsb->id));

	dsb_ctrl = intel_de_read(dev_priv, DSB_CTRL(pipe, dsb->id));

	if (DSB_STATUS & dsb_ctrl) {

		DRM_DEBUG_KMS("DSB engine is busy.\n");

		return false;

	}



	dsb_ctrl |= DSB_ENABLE;

	I915_WRITE(DSB_CTRL(pipe, dsb->id), dsb_ctrl);

	intel_de_write(dev_priv, DSB_CTRL(pipe, dsb->id), dsb_ctrl);



	POSTING_READ(DSB_CTRL(pipe, dsb->id));

	intel_de_posting_read(dev_priv, DSB_CTRL(pipe, dsb->id));

	return true;

}
@@ -70,16 +70,16 @@ static inline bool intel_dsb_disable_engine(struct intel_dsb *dsb) 
	enum pipe pipe = crtc->pipe;

	u32 dsb_ctrl;



	dsb_ctrl = I915_READ(DSB_CTRL(pipe, dsb->id));

	dsb_ctrl = intel_de_read(dev_priv, DSB_CTRL(pipe, dsb->id));

	if (DSB_STATUS & dsb_ctrl) {

		DRM_DEBUG_KMS("DSB engine is busy.\n");

		return false;

	}



	dsb_ctrl &= ~DSB_ENABLE;

	I915_WRITE(DSB_CTRL(pipe, dsb->id), dsb_ctrl);

	intel_de_write(dev_priv, DSB_CTRL(pipe, dsb->id), dsb_ctrl);



	POSTING_READ(DSB_CTRL(pipe, dsb->id));

	intel_de_posting_read(dev_priv, DSB_CTRL(pipe, dsb->id));

	return true;

}
@@ -198,7 +198,7 @@ void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg, 
	u32 reg_val;



	if (!buf) {

		I915_WRITE(reg, val);

		intel_de_write(dev_priv, reg, val);

		return;

	}
@@ -272,7 +272,7 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val) 
	u32 *buf = dsb->cmd_buf;



	if (!buf) {

		I915_WRITE(reg, val);

		intel_de_write(dev_priv, reg, val);

		return;

	}
@@ -313,7 +313,8 @@ void intel_dsb_commit(struct intel_dsb *dsb) 
		DRM_ERROR("HEAD_PTR write failed - dsb engine is busy.\n");

		goto reset;

	}

	I915_WRITE(DSB_HEAD(pipe, dsb->id), i915_ggtt_offset(dsb->vma));

	intel_de_write(dev_priv, DSB_HEAD(pipe, dsb->id),

		       i915_ggtt_offset(dsb->vma));



	tail = ALIGN(dsb->free_pos * 4, CACHELINE_BYTES);

	if (tail > dsb->free_pos * 4)
@@ -326,7 +327,8 @@ void intel_dsb_commit(struct intel_dsb *dsb) 
	}

	DRM_DEBUG_KMS("DSB execution started - head 0x%x, tail 0x%x\n",

		      i915_ggtt_offset(dsb->vma), tail);

	I915_WRITE(DSB_TAIL(pipe, dsb->id), i915_ggtt_offset(dsb->vma) + tail);

	intel_de_write(dev_priv, DSB_TAIL(pipe, dsb->id),

		       i915_ggtt_offset(dsb->vma) + tail);

	if (wait_for(!is_dsb_busy(dsb), 1)) {

		DRM_ERROR("Timed out waiting for DSB workload completion.\n");

		goto reset;

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