Commit 7cc7e935 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'x86-misc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull misc x86 updates from Ingo Molnar:

 - extend the decoder maps with CET instructions

 - fix !vDSO corner cases

* 'x86-misc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  perf/tests: Add CET instructions to the new instructions test
  x86/insn: Add Control-flow Enforcement (CET) instructions to the opcode map
  selftests/x86/ptrace_syscall_32: Fix no-vDSO segfault
  selftests/x86/vdso: Fix no-vDSO segfaults
parents d0be2d53 1032f326

arch/x86/lib/x86-opcode-map.txt

+11 −6
Original line number Diff line number Diff line
@@ -366,7 +366,7 @@ AVXcode: 1 
1b: BNDCN Gv,Ev (F2) | BNDMOV Ev,Gv (66) | BNDMK Gv,Ev (F3) | BNDSTX Ev,Gv

1c: Grp20 (1A),(1C)

1d:

1e:

1e: Grp21 (1A)

1f: NOP Ev

# 0x0f 0x20-0x2f

20: MOV Rd,Cd
@@ -803,8 +803,8 @@ f0: MOVBE Gy,My | MOVBE Gw,Mw (66) | CRC32 Gd,Eb (F2) | CRC32 Gd,Eb (66&F2) 
f1: MOVBE My,Gy | MOVBE Mw,Gw (66) | CRC32 Gd,Ey (F2) | CRC32 Gd,Ew (66&F2)

f2: ANDN Gy,By,Ey (v)

f3: Grp17 (1A)

f5: BZHI Gy,Ey,By (v) | PEXT Gy,By,Ey (F3),(v) | PDEP Gy,By,Ey (F2),(v)

f6: ADCX Gy,Ey (66) | ADOX Gy,Ey (F3) | MULX By,Gy,rDX,Ey (F2),(v)

f5: BZHI Gy,Ey,By (v) | PEXT Gy,By,Ey (F3),(v) | PDEP Gy,By,Ey (F2),(v) | WRUSSD/Q My,Gy (66)

f6: ADCX Gy,Ey (66) | ADOX Gy,Ey (F3) | MULX By,Gy,rDX,Ey (F2),(v) | WRSSD/Q My,Gy

f7: BEXTR Gy,Ey,By (v) | SHLX Gy,Ey,By (66),(v) | SARX Gy,Ey,By (F3),(v) | SHRX Gy,Ey,By (F2),(v)

f8: MOVDIR64B Gv,Mdqq (66) | ENQCMD Gv,Mdqq (F2) | ENQCMDS Gv,Mdqq (F3)

f9: MOVDIRI My,Gy
@@ -970,7 +970,7 @@ GrpTable: Grp7 
2: LGDT Ms | XGETBV (000),(11B) | XSETBV (001),(11B) | VMFUNC (100),(11B) | XEND (101)(11B) | XTEST (110)(11B) | ENCLU (111),(11B)

3: LIDT Ms

4: SMSW Mw/Rv

5: rdpkru (110),(11B) | wrpkru (111),(11B)

5: rdpkru (110),(11B) | wrpkru (111),(11B) | SAVEPREVSSP (F3),(010),(11B) | RSTORSSP Mq (F3) | SETSSBSY (F3),(000),(11B)

6: LMSW Ew

7: INVLPG Mb | SWAPGS (o64),(000),(11B) | RDTSCP (001),(11B)

EndTable
@@ -1041,8 +1041,8 @@ GrpTable: Grp15 
2: vldmxcsr Md (v1) | WRFSBASE Ry (F3),(11B)

3: vstmxcsr Md (v1) | WRGSBASE Ry (F3),(11B)

4: XSAVE | ptwrite Ey (F3),(11B)

5: XRSTOR | lfence (11B)

6: XSAVEOPT | clwb (66) | mfence (11B) | TPAUSE Rd (66),(11B) | UMONITOR Rv (F3),(11B) | UMWAIT Rd (F2),(11B)

5: XRSTOR | lfence (11B) | INCSSPD/Q Ry (F3),(11B)

6: XSAVEOPT | clwb (66) | mfence (11B) | TPAUSE Rd (66),(11B) | UMONITOR Rv (F3),(11B) | UMWAIT Rd (F2),(11B) | CLRSSBSY Mq (F3)

7: clflush | clflushopt (66) | sfence (11B)

EndTable
@@ -1077,6 +1077,11 @@ GrpTable: Grp20 
0: cldemote Mb

EndTable



GrpTable: Grp21

1: RDSSPD/Q Ry (F3),(11B)

7: ENDBR64 (F3),(010),(11B) | ENDBR32 (F3),(011),(11B)

EndTable



# AMD's Prefetch Group

GrpTable: GrpP

0: PREFETCH

tools/arch/x86/lib/x86-opcode-map.txt

+11 −6
Original line number Diff line number Diff line
@@ -366,7 +366,7 @@ AVXcode: 1 
1b: BNDCN Gv,Ev (F2) | BNDMOV Ev,Gv (66) | BNDMK Gv,Ev (F3) | BNDSTX Ev,Gv

1c: Grp20 (1A),(1C)

1d:

1e:

1e: Grp21 (1A)

1f: NOP Ev

# 0x0f 0x20-0x2f

20: MOV Rd,Cd
@@ -803,8 +803,8 @@ f0: MOVBE Gy,My | MOVBE Gw,Mw (66) | CRC32 Gd,Eb (F2) | CRC32 Gd,Eb (66&F2) 
f1: MOVBE My,Gy | MOVBE Mw,Gw (66) | CRC32 Gd,Ey (F2) | CRC32 Gd,Ew (66&F2)

f2: ANDN Gy,By,Ey (v)

f3: Grp17 (1A)

f5: BZHI Gy,Ey,By (v) | PEXT Gy,By,Ey (F3),(v) | PDEP Gy,By,Ey (F2),(v)

f6: ADCX Gy,Ey (66) | ADOX Gy,Ey (F3) | MULX By,Gy,rDX,Ey (F2),(v)

f5: BZHI Gy,Ey,By (v) | PEXT Gy,By,Ey (F3),(v) | PDEP Gy,By,Ey (F2),(v) | WRUSSD/Q My,Gy (66)

f6: ADCX Gy,Ey (66) | ADOX Gy,Ey (F3) | MULX By,Gy,rDX,Ey (F2),(v) | WRSSD/Q My,Gy

f7: BEXTR Gy,Ey,By (v) | SHLX Gy,Ey,By (66),(v) | SARX Gy,Ey,By (F3),(v) | SHRX Gy,Ey,By (F2),(v)

f8: MOVDIR64B Gv,Mdqq (66) | ENQCMD Gv,Mdqq (F2) | ENQCMDS Gv,Mdqq (F3)

f9: MOVDIRI My,Gy
@@ -970,7 +970,7 @@ GrpTable: Grp7 
2: LGDT Ms | XGETBV (000),(11B) | XSETBV (001),(11B) | VMFUNC (100),(11B) | XEND (101)(11B) | XTEST (110)(11B) | ENCLU (111),(11B)

3: LIDT Ms

4: SMSW Mw/Rv

5: rdpkru (110),(11B) | wrpkru (111),(11B)

5: rdpkru (110),(11B) | wrpkru (111),(11B) | SAVEPREVSSP (F3),(010),(11B) | RSTORSSP Mq (F3) | SETSSBSY (F3),(000),(11B)

6: LMSW Ew

7: INVLPG Mb | SWAPGS (o64),(000),(11B) | RDTSCP (001),(11B)

EndTable
@@ -1041,8 +1041,8 @@ GrpTable: Grp15 
2: vldmxcsr Md (v1) | WRFSBASE Ry (F3),(11B)

3: vstmxcsr Md (v1) | WRGSBASE Ry (F3),(11B)

4: XSAVE | ptwrite Ey (F3),(11B)

5: XRSTOR | lfence (11B)

6: XSAVEOPT | clwb (66) | mfence (11B) | TPAUSE Rd (66),(11B) | UMONITOR Rv (F3),(11B) | UMWAIT Rd (F2),(11B)

5: XRSTOR | lfence (11B) | INCSSPD/Q Ry (F3),(11B)

6: XSAVEOPT | clwb (66) | mfence (11B) | TPAUSE Rd (66),(11B) | UMONITOR Rv (F3),(11B) | UMWAIT Rd (F2),(11B) | CLRSSBSY Mq (F3)

7: clflush | clflushopt (66) | sfence (11B)

EndTable
@@ -1077,6 +1077,11 @@ GrpTable: Grp20 
0: cldemote Mb

EndTable



GrpTable: Grp21

1: RDSSPD/Q Ry (F3),(11B)

7: ENDBR64 (F3),(010),(11B) | ENDBR32 (F3),(011),(11B)

EndTable



# AMD's Prefetch Group

GrpTable: GrpP

0: PREFETCH

tools/perf/arch/x86/tests/insn-x86-dat-32.c

+112 −0
Original line number Diff line number Diff line
@@ -2085,6 +2085,118 @@ 
"67 f3 0f 38 f8 1c    \tenqcmds (%si),%bx",},

{{0x67, 0xf3, 0x0f, 0x38, 0xf8, 0x8c, 0x34, 0x12, }, 8, 0, "", "",

"67 f3 0f 38 f8 8c 34 12 \tenqcmds 0x1234(%si),%cx",},

{{0xf3, 0x0f, 0xae, 0xe8, }, 4, 0, "", "",

"f3 0f ae e8          \tincsspd %eax",},

{{0x0f, 0xae, 0x28, }, 3, 0, "", "",

"0f ae 28             \txrstor (%eax)",},

{{0x0f, 0xae, 0x2d, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",

"0f ae 2d 78 56 34 12 \txrstor 0x12345678",},

{{0x0f, 0xae, 0xac, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",

"0f ae ac c8 78 56 34 12 \txrstor 0x12345678(%eax,%ecx,8)",},

{{0x0f, 0xae, 0xe8, }, 3, 0, "", "",

"0f ae e8             \tlfence ",},

{{0xf3, 0x0f, 0x1e, 0xc8, }, 4, 0, "", "",

"f3 0f 1e c8          \trdsspd %eax",},

{{0xf3, 0x0f, 0x01, 0xea, }, 4, 0, "", "",

"f3 0f 01 ea          \tsaveprevssp ",},

{{0xf3, 0x0f, 0x01, 0x28, }, 4, 0, "", "",

"f3 0f 01 28          \trstorssp (%eax)",},

{{0xf3, 0x0f, 0x01, 0x2d, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",

"f3 0f 01 2d 78 56 34 12 \trstorssp 0x12345678",},

{{0xf3, 0x0f, 0x01, 0xac, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",

"f3 0f 01 ac c8 78 56 34 12 \trstorssp 0x12345678(%eax,%ecx,8)",},

{{0x0f, 0x38, 0xf6, 0x08, }, 4, 0, "", "",

"0f 38 f6 08          \twrssd  %ecx,(%eax)",},

{{0x0f, 0x38, 0xf6, 0x15, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",

"0f 38 f6 15 78 56 34 12 \twrssd  %edx,0x12345678",},

{{0x0f, 0x38, 0xf6, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",

"0f 38 f6 94 c8 78 56 34 12 \twrssd  %edx,0x12345678(%eax,%ecx,8)",},

{{0x66, 0x0f, 0x38, 0xf5, 0x08, }, 5, 0, "", "",

"66 0f 38 f5 08       \twrussd %ecx,(%eax)",},

{{0x66, 0x0f, 0x38, 0xf5, 0x15, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",

"66 0f 38 f5 15 78 56 34 12 \twrussd %edx,0x12345678",},

{{0x66, 0x0f, 0x38, 0xf5, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",

"66 0f 38 f5 94 c8 78 56 34 12 \twrussd %edx,0x12345678(%eax,%ecx,8)",},

{{0xf3, 0x0f, 0x01, 0xe8, }, 4, 0, "", "",

"f3 0f 01 e8          \tsetssbsy ",},

{{0x0f, 0x01, 0xee, }, 3, 0, "", "",

"0f 01 ee             \trdpkru ",},

{{0x0f, 0x01, 0xef, }, 3, 0, "", "",

"0f 01 ef             \twrpkru ",},

{{0xf3, 0x0f, 0xae, 0x30, }, 4, 0, "", "",

"f3 0f ae 30          \tclrssbsy (%eax)",},

{{0xf3, 0x0f, 0xae, 0x35, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",

"f3 0f ae 35 78 56 34 12 \tclrssbsy 0x12345678",},

{{0xf3, 0x0f, 0xae, 0xb4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",

"f3 0f ae b4 c8 78 56 34 12 \tclrssbsy 0x12345678(%eax,%ecx,8)",},

{{0xf3, 0x0f, 0x1e, 0xfb, }, 4, 0, "", "",

"f3 0f 1e fb          \tendbr32 ",},

{{0xf3, 0x0f, 0x1e, 0xfa, }, 4, 0, "", "",

"f3 0f 1e fa          \tendbr64 ",},

{{0xff, 0xd0, }, 2, 0, "call", "indirect",

"ff d0                \tcall   *%eax",},

{{0xff, 0x10, }, 2, 0, "call", "indirect",

"ff 10                \tcall   *(%eax)",},

{{0xff, 0x15, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "call", "indirect",

"ff 15 78 56 34 12    \tcall   *0x12345678",},

{{0xff, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "call", "indirect",

"ff 94 c8 78 56 34 12 \tcall   *0x12345678(%eax,%ecx,8)",},

{{0xf2, 0xff, 0xd0, }, 3, 0, "call", "indirect",

"f2 ff d0             \tbnd call *%eax",},

{{0xf2, 0xff, 0x10, }, 3, 0, "call", "indirect",

"f2 ff 10             \tbnd call *(%eax)",},

{{0xf2, 0xff, 0x15, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "call", "indirect",

"f2 ff 15 78 56 34 12 \tbnd call *0x12345678",},

{{0xf2, 0xff, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "call", "indirect",

"f2 ff 94 c8 78 56 34 12 \tbnd call *0x12345678(%eax,%ecx,8)",},

{{0x3e, 0xff, 0xd0, }, 3, 0, "call", "indirect",

"3e ff d0             \tnotrack call *%eax",},

{{0x3e, 0xff, 0x10, }, 3, 0, "call", "indirect",

"3e ff 10             \tnotrack call *(%eax)",},

{{0x3e, 0xff, 0x15, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "call", "indirect",

"3e ff 15 78 56 34 12 \tnotrack call *0x12345678",},

{{0x3e, 0xff, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "call", "indirect",

"3e ff 94 c8 78 56 34 12 \tnotrack call *0x12345678(%eax,%ecx,8)",},

{{0x3e, 0xf2, 0xff, 0xd0, }, 4, 0, "call", "indirect",

"3e f2 ff d0          \tnotrack bnd call *%eax",},

{{0x3e, 0xf2, 0xff, 0x10, }, 4, 0, "call", "indirect",

"3e f2 ff 10          \tnotrack bnd call *(%eax)",},

{{0x3e, 0xf2, 0xff, 0x15, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "call", "indirect",

"3e f2 ff 15 78 56 34 12 \tnotrack bnd call *0x12345678",},

{{0x3e, 0xf2, 0xff, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "call", "indirect",

"3e f2 ff 94 c8 78 56 34 12 \tnotrack bnd call *0x12345678(%eax,%ecx,8)",},

{{0xff, 0xe0, }, 2, 0, "jmp", "indirect",

"ff e0                \tjmp    *%eax",},

{{0xff, 0x20, }, 2, 0, "jmp", "indirect",

"ff 20                \tjmp    *(%eax)",},

{{0xff, 0x25, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "jmp", "indirect",

"ff 25 78 56 34 12    \tjmp    *0x12345678",},

{{0xff, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "jmp", "indirect",

"ff a4 c8 78 56 34 12 \tjmp    *0x12345678(%eax,%ecx,8)",},

{{0xf2, 0xff, 0xe0, }, 3, 0, "jmp", "indirect",

"f2 ff e0             \tbnd jmp *%eax",},

{{0xf2, 0xff, 0x20, }, 3, 0, "jmp", "indirect",

"f2 ff 20             \tbnd jmp *(%eax)",},

{{0xf2, 0xff, 0x25, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "jmp", "indirect",

"f2 ff 25 78 56 34 12 \tbnd jmp *0x12345678",},

{{0xf2, 0xff, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "jmp", "indirect",

"f2 ff a4 c8 78 56 34 12 \tbnd jmp *0x12345678(%eax,%ecx,8)",},

{{0x3e, 0xff, 0xe0, }, 3, 0, "jmp", "indirect",

"3e ff e0             \tnotrack jmp *%eax",},

{{0x3e, 0xff, 0x20, }, 3, 0, "jmp", "indirect",

"3e ff 20             \tnotrack jmp *(%eax)",},

{{0x3e, 0xff, 0x25, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "jmp", "indirect",

"3e ff 25 78 56 34 12 \tnotrack jmp *0x12345678",},

{{0x3e, 0xff, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "jmp", "indirect",

"3e ff a4 c8 78 56 34 12 \tnotrack jmp *0x12345678(%eax,%ecx,8)",},

{{0x3e, 0xf2, 0xff, 0xe0, }, 4, 0, "jmp", "indirect",

"3e f2 ff e0          \tnotrack bnd jmp *%eax",},

{{0x3e, 0xf2, 0xff, 0x20, }, 4, 0, "jmp", "indirect",

"3e f2 ff 20          \tnotrack bnd jmp *(%eax)",},

{{0x3e, 0xf2, 0xff, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "jmp", "indirect",

"3e f2 ff 25 78 56 34 12 \tnotrack bnd jmp *0x12345678",},

{{0x3e, 0xf2, 0xff, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "jmp", "indirect",

"3e f2 ff a4 c8 78 56 34 12 \tnotrack bnd jmp *0x12345678(%eax,%ecx,8)",},

{{0x0f, 0x01, 0xcf, }, 3, 0, "", "",

"0f 01 cf             \tencls  ",},

{{0x0f, 0x01, 0xd7, }, 3, 0, "", "",

tools/perf/arch/x86/tests/insn-x86-dat-64.c

+196 −0
Original line number Diff line number Diff line
@@ -2263,6 +2263,202 @@ 
"67 f3 0f 38 f8 18    \tenqcmds (%eax),%ebx",},

{{0x67, 0xf3, 0x0f, 0x38, 0xf8, 0x88, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",

"67 f3 0f 38 f8 88 78 56 34 12 \tenqcmds 0x12345678(%eax),%ecx",},

{{0xf3, 0x0f, 0xae, 0xe8, }, 4, 0, "", "",

"f3 0f ae e8          \tincsspd %eax",},

{{0xf3, 0x41, 0x0f, 0xae, 0xe8, }, 5, 0, "", "",

"f3 41 0f ae e8       \tincsspd %r8d",},

{{0xf3, 0x48, 0x0f, 0xae, 0xe8, }, 5, 0, "", "",

"f3 48 0f ae e8       \tincsspq %rax",},

{{0xf3, 0x49, 0x0f, 0xae, 0xe8, }, 5, 0, "", "",

"f3 49 0f ae e8       \tincsspq %r8",},

{{0x0f, 0xae, 0x28, }, 3, 0, "", "",

"0f ae 28             \txrstor (%rax)",},

{{0x41, 0x0f, 0xae, 0x28, }, 4, 0, "", "",

"41 0f ae 28          \txrstor (%r8)",},

{{0x0f, 0xae, 0x2c, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",

"0f ae 2c 25 78 56 34 12 \txrstor 0x12345678",},

{{0x0f, 0xae, 0xac, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",

"0f ae ac c8 78 56 34 12 \txrstor 0x12345678(%rax,%rcx,8)",},

{{0x41, 0x0f, 0xae, 0xac, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",

"41 0f ae ac c8 78 56 34 12 \txrstor 0x12345678(%r8,%rcx,8)",},

{{0x0f, 0xae, 0xe8, }, 3, 0, "", "",

"0f ae e8             \tlfence ",},

{{0xf3, 0x0f, 0x1e, 0xc8, }, 4, 0, "", "",

"f3 0f 1e c8          \trdsspd %eax",},

{{0xf3, 0x41, 0x0f, 0x1e, 0xc8, }, 5, 0, "", "",

"f3 41 0f 1e c8       \trdsspd %r8d",},

{{0xf3, 0x48, 0x0f, 0x1e, 0xc8, }, 5, 0, "", "",

"f3 48 0f 1e c8       \trdsspq %rax",},

{{0xf3, 0x49, 0x0f, 0x1e, 0xc8, }, 5, 0, "", "",

"f3 49 0f 1e c8       \trdsspq %r8",},

{{0xf3, 0x0f, 0x01, 0xea, }, 4, 0, "", "",

"f3 0f 01 ea          \tsaveprevssp ",},

{{0xf3, 0x0f, 0x01, 0x28, }, 4, 0, "", "",

"f3 0f 01 28          \trstorssp (%rax)",},

{{0xf3, 0x41, 0x0f, 0x01, 0x28, }, 5, 0, "", "",

"f3 41 0f 01 28       \trstorssp (%r8)",},

{{0xf3, 0x0f, 0x01, 0x2c, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",

"f3 0f 01 2c 25 78 56 34 12 \trstorssp 0x12345678",},

{{0xf3, 0x0f, 0x01, 0xac, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",

"f3 0f 01 ac c8 78 56 34 12 \trstorssp 0x12345678(%rax,%rcx,8)",},

{{0xf3, 0x41, 0x0f, 0x01, 0xac, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",

"f3 41 0f 01 ac c8 78 56 34 12 \trstorssp 0x12345678(%r8,%rcx,8)",},

{{0x0f, 0x38, 0xf6, 0x08, }, 4, 0, "", "",

"0f 38 f6 08          \twrssd  %ecx,(%rax)",},

{{0x41, 0x0f, 0x38, 0xf6, 0x10, }, 5, 0, "", "",

"41 0f 38 f6 10       \twrssd  %edx,(%r8)",},

{{0x0f, 0x38, 0xf6, 0x14, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",

"0f 38 f6 14 25 78 56 34 12 \twrssd  %edx,0x12345678",},

{{0x0f, 0x38, 0xf6, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",

"0f 38 f6 94 c8 78 56 34 12 \twrssd  %edx,0x12345678(%rax,%rcx,8)",},

{{0x41, 0x0f, 0x38, 0xf6, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",

"41 0f 38 f6 94 c8 78 56 34 12 \twrssd  %edx,0x12345678(%r8,%rcx,8)",},

{{0x48, 0x0f, 0x38, 0xf6, 0x08, }, 5, 0, "", "",

"48 0f 38 f6 08       \twrssq  %rcx,(%rax)",},

{{0x49, 0x0f, 0x38, 0xf6, 0x10, }, 5, 0, "", "",

"49 0f 38 f6 10       \twrssq  %rdx,(%r8)",},

{{0x48, 0x0f, 0x38, 0xf6, 0x14, 0x25, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",

"48 0f 38 f6 14 25 78 56 34 12 \twrssq  %rdx,0x12345678",},

{{0x48, 0x0f, 0x38, 0xf6, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",

"48 0f 38 f6 94 c8 78 56 34 12 \twrssq  %rdx,0x12345678(%rax,%rcx,8)",},

{{0x49, 0x0f, 0x38, 0xf6, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",

"49 0f 38 f6 94 c8 78 56 34 12 \twrssq  %rdx,0x12345678(%r8,%rcx,8)",},

{{0x66, 0x0f, 0x38, 0xf5, 0x08, }, 5, 0, "", "",

"66 0f 38 f5 08       \twrussd %ecx,(%rax)",},

{{0x66, 0x41, 0x0f, 0x38, 0xf5, 0x10, }, 6, 0, "", "",

"66 41 0f 38 f5 10    \twrussd %edx,(%r8)",},

{{0x66, 0x0f, 0x38, 0xf5, 0x14, 0x25, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",

"66 0f 38 f5 14 25 78 56 34 12 \twrussd %edx,0x12345678",},

{{0x66, 0x0f, 0x38, 0xf5, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",

"66 0f 38 f5 94 c8 78 56 34 12 \twrussd %edx,0x12345678(%rax,%rcx,8)",},

{{0x66, 0x41, 0x0f, 0x38, 0xf5, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",

"66 41 0f 38 f5 94 c8 78 56 34 12 \twrussd %edx,0x12345678(%r8,%rcx,8)",},

{{0x66, 0x48, 0x0f, 0x38, 0xf5, 0x08, }, 6, 0, "", "",

"66 48 0f 38 f5 08    \twrussq %rcx,(%rax)",},

{{0x66, 0x49, 0x0f, 0x38, 0xf5, 0x10, }, 6, 0, "", "",

"66 49 0f 38 f5 10    \twrussq %rdx,(%r8)",},

{{0x66, 0x48, 0x0f, 0x38, 0xf5, 0x14, 0x25, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",

"66 48 0f 38 f5 14 25 78 56 34 12 \twrussq %rdx,0x12345678",},

{{0x66, 0x48, 0x0f, 0x38, 0xf5, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",

"66 48 0f 38 f5 94 c8 78 56 34 12 \twrussq %rdx,0x12345678(%rax,%rcx,8)",},

{{0x66, 0x49, 0x0f, 0x38, 0xf5, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",

"66 49 0f 38 f5 94 c8 78 56 34 12 \twrussq %rdx,0x12345678(%r8,%rcx,8)",},

{{0xf3, 0x0f, 0x01, 0xe8, }, 4, 0, "", "",

"f3 0f 01 e8          \tsetssbsy ",},

{{0x0f, 0x01, 0xee, }, 3, 0, "", "",

"0f 01 ee             \trdpkru ",},

{{0x0f, 0x01, 0xef, }, 3, 0, "", "",

"0f 01 ef             \twrpkru ",},

{{0xf3, 0x0f, 0xae, 0x30, }, 4, 0, "", "",

"f3 0f ae 30          \tclrssbsy (%rax)",},

{{0xf3, 0x41, 0x0f, 0xae, 0x30, }, 5, 0, "", "",

"f3 41 0f ae 30       \tclrssbsy (%r8)",},

{{0xf3, 0x0f, 0xae, 0x34, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",

"f3 0f ae 34 25 78 56 34 12 \tclrssbsy 0x12345678",},

{{0xf3, 0x0f, 0xae, 0xb4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",

"f3 0f ae b4 c8 78 56 34 12 \tclrssbsy 0x12345678(%rax,%rcx,8)",},

{{0xf3, 0x41, 0x0f, 0xae, 0xb4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",

"f3 41 0f ae b4 c8 78 56 34 12 \tclrssbsy 0x12345678(%r8,%rcx,8)",},

{{0xf3, 0x0f, 0x1e, 0xfb, }, 4, 0, "", "",

"f3 0f 1e fb          \tendbr32 ",},

{{0xf3, 0x0f, 0x1e, 0xfa, }, 4, 0, "", "",

"f3 0f 1e fa          \tendbr64 ",},

{{0xff, 0xd0, }, 2, 0, "call", "indirect",

"ff d0                \tcallq  *%rax",},

{{0xff, 0x10, }, 2, 0, "call", "indirect",

"ff 10                \tcallq  *(%rax)",},

{{0x41, 0xff, 0x10, }, 3, 0, "call", "indirect",

"41 ff 10             \tcallq  *(%r8)",},

{{0xff, 0x14, 0x25, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "call", "indirect",

"ff 14 25 78 56 34 12 \tcallq  *0x12345678",},

{{0xff, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "call", "indirect",

"ff 94 c8 78 56 34 12 \tcallq  *0x12345678(%rax,%rcx,8)",},

{{0x41, 0xff, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "call", "indirect",

"41 ff 94 c8 78 56 34 12 \tcallq  *0x12345678(%r8,%rcx,8)",},

{{0xf2, 0xff, 0xd0, }, 3, 0, "call", "indirect",

"f2 ff d0             \tbnd callq *%rax",},

{{0xf2, 0xff, 0x10, }, 3, 0, "call", "indirect",

"f2 ff 10             \tbnd callq *(%rax)",},

{{0xf2, 0x41, 0xff, 0x10, }, 4, 0, "call", "indirect",

"f2 41 ff 10          \tbnd callq *(%r8)",},

{{0xf2, 0xff, 0x14, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "call", "indirect",

"f2 ff 14 25 78 56 34 12 \tbnd callq *0x12345678",},

{{0xf2, 0xff, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "call", "indirect",

"f2 ff 94 c8 78 56 34 12 \tbnd callq *0x12345678(%rax,%rcx,8)",},

{{0xf2, 0x41, 0xff, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "call", "indirect",

"f2 41 ff 94 c8 78 56 34 12 \tbnd callq *0x12345678(%r8,%rcx,8)",},

{{0x3e, 0xff, 0xd0, }, 3, 0, "call", "indirect",

"3e ff d0             \tnotrack callq *%rax",},

{{0x3e, 0xff, 0x10, }, 3, 0, "call", "indirect",

"3e ff 10             \tnotrack callq *(%rax)",},

{{0x3e, 0x41, 0xff, 0x10, }, 4, 0, "call", "indirect",

"3e 41 ff 10          \tnotrack callq *(%r8)",},

{{0x3e, 0xff, 0x14, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "call", "indirect",

"3e ff 14 25 78 56 34 12 \tnotrack callq *0x12345678",},

{{0x3e, 0xff, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "call", "indirect",

"3e ff 94 c8 78 56 34 12 \tnotrack callq *0x12345678(%rax,%rcx,8)",},

{{0x3e, 0x41, 0xff, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "call", "indirect",

"3e 41 ff 94 c8 78 56 34 12 \tnotrack callq *0x12345678(%r8,%rcx,8)",},

{{0x3e, 0xf2, 0xff, 0xd0, }, 4, 0, "call", "indirect",

"3e f2 ff d0          \tnotrack bnd callq *%rax",},

{{0x3e, 0xf2, 0xff, 0x10, }, 4, 0, "call", "indirect",

"3e f2 ff 10          \tnotrack bnd callq *(%rax)",},

{{0x3e, 0xf2, 0x41, 0xff, 0x10, }, 5, 0, "call", "indirect",

"3e f2 41 ff 10       \tnotrack bnd callq *(%r8)",},

{{0x3e, 0xf2, 0xff, 0x14, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "call", "indirect",

"3e f2 ff 14 25 78 56 34 12 \tnotrack bnd callq *0x12345678",},

{{0x3e, 0xf2, 0xff, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "call", "indirect",

"3e f2 ff 94 c8 78 56 34 12 \tnotrack bnd callq *0x12345678(%rax,%rcx,8)",},

{{0x3e, 0xf2, 0x41, 0xff, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "call", "indirect",

"3e f2 41 ff 94 c8 78 56 34 12 \tnotrack bnd callq *0x12345678(%r8,%rcx,8)",},

{{0xff, 0xe0, }, 2, 0, "jmp", "indirect",

"ff e0                \tjmpq   *%rax",},

{{0xff, 0x20, }, 2, 0, "jmp", "indirect",

"ff 20                \tjmpq   *(%rax)",},

{{0x41, 0xff, 0x20, }, 3, 0, "jmp", "indirect",

"41 ff 20             \tjmpq   *(%r8)",},

{{0xff, 0x24, 0x25, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "jmp", "indirect",

"ff 24 25 78 56 34 12 \tjmpq   *0x12345678",},

{{0xff, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "jmp", "indirect",

"ff a4 c8 78 56 34 12 \tjmpq   *0x12345678(%rax,%rcx,8)",},

{{0x41, 0xff, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "jmp", "indirect",

"41 ff a4 c8 78 56 34 12 \tjmpq   *0x12345678(%r8,%rcx,8)",},

{{0xf2, 0xff, 0xe0, }, 3, 0, "jmp", "indirect",

"f2 ff e0             \tbnd jmpq *%rax",},

{{0xf2, 0xff, 0x20, }, 3, 0, "jmp", "indirect",

"f2 ff 20             \tbnd jmpq *(%rax)",},

{{0xf2, 0x41, 0xff, 0x20, }, 4, 0, "jmp", "indirect",

"f2 41 ff 20          \tbnd jmpq *(%r8)",},

{{0xf2, 0xff, 0x24, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "jmp", "indirect",

"f2 ff 24 25 78 56 34 12 \tbnd jmpq *0x12345678",},

{{0xf2, 0xff, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "jmp", "indirect",

"f2 ff a4 c8 78 56 34 12 \tbnd jmpq *0x12345678(%rax,%rcx,8)",},

{{0xf2, 0x41, 0xff, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "jmp", "indirect",

"f2 41 ff a4 c8 78 56 34 12 \tbnd jmpq *0x12345678(%r8,%rcx,8)",},

{{0x3e, 0xff, 0xe0, }, 3, 0, "jmp", "indirect",

"3e ff e0             \tnotrack jmpq *%rax",},

{{0x3e, 0xff, 0x20, }, 3, 0, "jmp", "indirect",

"3e ff 20             \tnotrack jmpq *(%rax)",},

{{0x3e, 0x41, 0xff, 0x20, }, 4, 0, "jmp", "indirect",

"3e 41 ff 20          \tnotrack jmpq *(%r8)",},

{{0x3e, 0xff, 0x24, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "jmp", "indirect",

"3e ff 24 25 78 56 34 12 \tnotrack jmpq *0x12345678",},

{{0x3e, 0xff, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "jmp", "indirect",

"3e ff a4 c8 78 56 34 12 \tnotrack jmpq *0x12345678(%rax,%rcx,8)",},

{{0x3e, 0x41, 0xff, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "jmp", "indirect",

"3e 41 ff a4 c8 78 56 34 12 \tnotrack jmpq *0x12345678(%r8,%rcx,8)",},

{{0x3e, 0xf2, 0xff, 0xe0, }, 4, 0, "jmp", "indirect",

"3e f2 ff e0          \tnotrack bnd jmpq *%rax",},

{{0x3e, 0xf2, 0xff, 0x20, }, 4, 0, "jmp", "indirect",

"3e f2 ff 20          \tnotrack bnd jmpq *(%rax)",},

{{0x3e, 0xf2, 0x41, 0xff, 0x20, }, 5, 0, "jmp", "indirect",

"3e f2 41 ff 20       \tnotrack bnd jmpq *(%r8)",},

{{0x3e, 0xf2, 0xff, 0x24, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "jmp", "indirect",

"3e f2 ff 24 25 78 56 34 12 \tnotrack bnd jmpq *0x12345678",},

{{0x3e, 0xf2, 0xff, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "jmp", "indirect",

"3e f2 ff a4 c8 78 56 34 12 \tnotrack bnd jmpq *0x12345678(%rax,%rcx,8)",},

{{0x3e, 0xf2, 0x41, 0xff, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "jmp", "indirect",

"3e f2 41 ff a4 c8 78 56 34 12 \tnotrack bnd jmpq *0x12345678(%r8,%rcx,8)",},

{{0x0f, 0x01, 0xcf, }, 3, 0, "", "",

"0f 01 cf             \tencls  ",},

{{0x0f, 0x01, 0xd7, }, 3, 0, "", "",

tools/perf/arch/x86/tests/insn-x86-dat-src.c

+236 −0

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