Commit 7cc373db authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'cxgb4-add-support-to-read-write-flash' 



Vishal Kulkarni says:

====================
cxgb4: add support to read/write flash

This series of patches adds support to read/write different binary images
of serial flash present in Chelsio terminator.

V2 changes:
Patch 1: No change
Patch 2: No change
Patch 3: Fix 4 compilation warnings reported by C=1, W=1 flags
Patch 4: No change
Patch 5: No change
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 0fb9fbab 17b332f4

drivers/net/ethernet/chelsio/cxgb4/cudbg_if.h

+2 −1
Original line number Diff line number Diff line
@@ -70,7 +70,8 @@ enum cudbg_dbg_entity_type { 
	CUDBG_HMA_INDIRECT = 67,

	CUDBG_HMA = 68,

	CUDBG_QDESC = 70,

	CUDBG_MAX_ENTITY = 71,

	CUDBG_FLASH = 71,

	CUDBG_MAX_ENTITY = 72,

};



struct cudbg_init {

drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c

+37 −0
Original line number Diff line number Diff line
@@ -3156,3 +3156,40 @@ out_free: 


	return rc;

}



int cudbg_collect_flash(struct cudbg_init *pdbg_init,

			struct cudbg_buffer *dbg_buff,

			struct cudbg_error *cudbg_err)

{

	struct adapter *padap = pdbg_init->adap;

	u32 count = padap->params.sf_size, n;

	struct cudbg_buffer temp_buff = {0};

	u32 addr, i;

	int rc;



	addr = FLASH_EXP_ROM_START;



	for (i = 0; i < count; i += SF_PAGE_SIZE) {

		n = min_t(u32, count - i, SF_PAGE_SIZE);



		rc = cudbg_get_buff(pdbg_init, dbg_buff, n, &temp_buff);

		if (rc) {

			cudbg_err->sys_warn = CUDBG_STATUS_PARTIAL_DATA;

			goto out;

		}

		rc = t4_read_flash(padap, addr, n, (u32 *)temp_buff.data, 0);

		if (rc)

			goto out;



		addr += (n * 4);

		rc = cudbg_write_and_release_buff(pdbg_init, &temp_buff,

						  dbg_buff);

		if (rc) {

			cudbg_err->sys_warn = CUDBG_STATUS_PARTIAL_DATA;

			goto out;

		}

	}



out:

	return rc;

}

drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.h

+3 −1
Original line number Diff line number Diff line
@@ -162,7 +162,9 @@ int cudbg_collect_hma_meminfo(struct cudbg_init *pdbg_init, 
int cudbg_collect_qdesc(struct cudbg_init *pdbg_init,

			struct cudbg_buffer *dbg_buff,

			struct cudbg_error *cudbg_err);



int cudbg_collect_flash(struct cudbg_init *pdbg_init,

			struct cudbg_buffer *dbg_buff,

			struct cudbg_error *cudbg_err);

struct cudbg_entity_hdr *cudbg_get_entity_hdr(void *outbuf, int i);

void cudbg_align_debug_buffer(struct cudbg_buffer *dbg_buff,

			      struct cudbg_entity_hdr *entity_hdr);

drivers/net/ethernet/chelsio/cxgb4/cxgb4.h

+67 −0
Original line number Diff line number Diff line
@@ -139,6 +139,64 @@ enum cc_fec { 
	FEC_BASER_RS  = 1 << 2   /* BaseR/Reed-Solomon */

};



enum {

	CXGB4_ETHTOOL_FLASH_FW = 1,

	CXGB4_ETHTOOL_FLASH_PHY = 2,

	CXGB4_ETHTOOL_FLASH_BOOT = 3,

	CXGB4_ETHTOOL_FLASH_BOOTCFG = 4

};



struct cxgb4_bootcfg_data {

	__le16 signature;

	__u8 reserved[2];

};



struct cxgb4_pcir_data {

	__le32 signature;	/* Signature. The string "PCIR" */

	__le16 vendor_id;	/* Vendor Identification */

	__le16 device_id;	/* Device Identification */

	__u8 vital_product[2];	/* Pointer to Vital Product Data */

	__u8 length[2];		/* PCIR Data Structure Length */

	__u8 revision;		/* PCIR Data Structure Revision */

	__u8 class_code[3];	/* Class Code */

	__u8 image_length[2];	/* Image Length. Multiple of 512B */

	__u8 code_revision[2];	/* Revision Level of Code/Data */

	__u8 code_type;

	__u8 indicator;

	__u8 reserved[2];

};



/* BIOS boot headers */

struct cxgb4_pci_exp_rom_header {

	__le16 signature;	/* ROM Signature. Should be 0xaa55 */

	__u8 reserved[22];	/* Reserved per processor Architecture data */

	__le16 pcir_offset;	/* Offset to PCI Data Structure */

};



/* Legacy PCI Expansion ROM Header */

struct legacy_pci_rom_hdr {

	__u8 signature[2];	/* ROM Signature. Should be 0xaa55 */

	__u8 size512;		/* Current Image Size in units of 512 bytes */

	__u8 initentry_point[4];

	__u8 cksum;		/* Checksum computed on the entire Image */

	__u8 reserved[16];	/* Reserved */

	__le16 pcir_offset;	/* Offset to PCI Data Struture */

};



#define CXGB4_HDR_CODE1 0x00

#define CXGB4_HDR_CODE2 0x03

#define CXGB4_HDR_INDI 0x80



/* BOOT constants */

enum {

	BOOT_CFG_SIG = 0x4243,

	BOOT_SIZE_INC = 512,

	BOOT_SIGNATURE = 0xaa55,

	BOOT_MIN_SIZE = sizeof(struct cxgb4_pci_exp_rom_header),

	BOOT_MAX_SIZE = 1024 * BOOT_SIZE_INC,

	PCIR_SIGNATURE = 0x52494350

};



struct port_stats {

	u64 tx_octets;            /* total # of octets in good frames */

	u64 tx_frames;            /* all good frames */
@@ -492,6 +550,11 @@ struct trace_params { 
	unsigned char port;

};



struct cxgb4_fw_data {

	__be32 signature;

	__u8 reserved[4];

};



/* Firmware Port Capabilities types. */



typedef u16 fw_port_cap16_t;	/* 16-bit Port Capabilities integral value */
@@ -1988,6 +2051,10 @@ void t4_register_netevent_notifier(void); 
int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port,

	      unsigned int devid, unsigned int offset,

	      unsigned int len, u8 *buf);

int t4_load_boot(struct adapter *adap, u8 *boot_data,

		 unsigned int boot_addr, unsigned int size);

int t4_load_bootcfg(struct adapter *adap,

		    const u8 *cfg_data, unsigned int size);

void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl);

void free_tx_desc(struct adapter *adap, struct sge_txq *q,

		  unsigned int n, bool unmap);

drivers/net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c

+14 −0
Original line number Diff line number Diff line
@@ -66,6 +66,10 @@ static const struct cxgb4_collect_entity cxgb4_collect_hw_dump[] = { 
	{ CUDBG_HMA_INDIRECT, cudbg_collect_hma_indirect },

};



static const struct cxgb4_collect_entity cxgb4_collect_flash_dump[] = {

	{ CUDBG_FLASH, cudbg_collect_flash },

};



static u32 cxgb4_get_entity_length(struct adapter *adap, u32 entity)

{

	struct cudbg_tcam tcam_region = { 0 };
@@ -330,6 +334,9 @@ u32 cxgb4_get_dump_length(struct adapter *adap, u32 flag) 
		}

	}



	if (flag & CXGB4_ETH_DUMP_FLASH)

		len += adap->params.sf_size;



	/* If compression is enabled, a smaller destination buffer is enough */

	wsize = cudbg_get_workspace_size();

	if (wsize && len > CUDBG_DUMP_BUFF_SIZE)
@@ -468,6 +475,13 @@ int cxgb4_cudbg_collect(struct adapter *adap, void *buf, u32 *buf_size, 
					   buf,

					   &total_size);



	if (flag & CXGB4_ETH_DUMP_FLASH)

		cxgb4_cudbg_collect_entity(&cudbg_init, &dbg_buff,

					   cxgb4_collect_flash_dump,

					   ARRAY_SIZE(cxgb4_collect_flash_dump),

					   buf,

					   &total_size);



	cudbg_free_compress_buff(&cudbg_init);

	cudbg_hdr->data_len = total_size;

	if (cudbg_init.compress_type != CUDBG_COMPRESSION_NONE)

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