irqchip/gic-v3: Configure all interrupts as non-secure Group-1 (7c9b9730) · Commits · 戴 / test

The GICv3 driver wrongly assumes that it runs on the non-secure side of a secure-enabled system, while it could be on a system with a single security state, or a GICv3 with GICD_CTLR.DS set. Either way, it is important to configure this properly, or interrupts will simply not be delivered on this HW. Cc: stable@vger.kernel.org Reported-by:

Peter Maydell <peter.maydell@linaro.org> Tested-by:

Peter Maydell <peter.maydell@linaro.org> Signed-off-by:

Marc Zyngier <marc.zyngier@arm.com>

drivers/irqchip/irq-gic-v3.c

+12 −0

Original line number	Diff line number	Diff line
		@@ -393,6 +393,15 @@ static void __init gic_dist_init(void)
		writel_relaxed(0, base + GICD_CTLR);
		gic_dist_wait_for_rwp();

		/*
		* Configure SPIs as non-secure Group-1. This will only matter
		* if the GIC only has a single security state. This will not
		* do the right thing if the kernel is running in secure mode,
		* but that's not the intended use case anyway.
		*/
		for (i = 32; i < gic_data.irq_nr; i += 32)
		writel_relaxed(~0, base + GICD_IGROUPR + i / 8);

		gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp);

		/* Enable distributor with ARE, Group1 */
		@@ -510,6 +519,9 @@ static void gic_cpu_init(void)

		rbase = gic_data_rdist_sgi_base();

		/* Configure SGIs/PPIs as non-secure Group-1 */
		writel_relaxed(~0, rbase + GICR_IGROUPR0);

		gic_cpu_config(rbase, gic_redist_wait_for_rwp);

		/* Give LPIs a spin */

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