Commit 7c42545c authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'linux-5.6' of git://github.com/skeggsb/linux into drm-fixes 



Nothing major here, another TU1xx modesetting fix, and hooking up
ACR/GR support on TU11x now that NVIDIA have made the firmware
available.

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Ben Skeggs <skeggsb@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ <CACAvsv64yBq4KHJ8D-5HQ5eeotApJSMiD+V2ut4f3BonUggf0Q@mail.gmail.com
parents ec0bd60a f287d3d1

drivers/gpu/drm/nouveau/dispnv50/wndw.c

+2 −0
Original line number Diff line number Diff line
@@ -458,6 +458,8 @@ nv50_wndw_atomic_check(struct drm_plane *plane, struct drm_plane_state *state) 
		asyw->clr.ntfy = armw->ntfy.handle != 0;

		asyw->clr.sema = armw->sema.handle != 0;

		asyw->clr.xlut = armw->xlut.handle != 0;

		if (asyw->clr.xlut && asyw->visible)

			asyw->set.xlut = asyw->xlut.handle != 0;

		asyw->clr.csc  = armw->csc.valid;

		if (wndw->func->image_clr)

			asyw->clr.image = armw->image.handle[0] != 0;

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

+4 −0
Original line number Diff line number Diff line
@@ -2579,6 +2579,7 @@ nv166_chipset = { 
static const struct nvkm_device_chip

nv167_chipset = {

	.name = "TU117",

	.acr = tu102_acr_new,

	.bar = tu102_bar_new,

	.bios = nvkm_bios_new,

	.bus = gf100_bus_new,
@@ -2607,6 +2608,7 @@ nv167_chipset = { 
	.disp = tu102_disp_new,

	.dma = gv100_dma_new,

	.fifo = tu102_fifo_new,

	.gr = tu102_gr_new,

	.nvdec[0] = gm107_nvdec_new,

	.nvenc[0] = gm107_nvenc_new,

	.sec2 = tu102_sec2_new,
@@ -2615,6 +2617,7 @@ nv167_chipset = { 
static const struct nvkm_device_chip

nv168_chipset = {

	.name = "TU116",

	.acr = tu102_acr_new,

	.bar = tu102_bar_new,

	.bios = nvkm_bios_new,

	.bus = gf100_bus_new,
@@ -2643,6 +2646,7 @@ nv168_chipset = { 
	.disp = tu102_disp_new,

	.dma = gv100_dma_new,

	.fifo = tu102_fifo_new,

	.gr = tu102_gr_new,

	.nvdec[0] = gm107_nvdec_new,

	.nvenc[0] = gm107_nvenc_new,

	.sec2 = tu102_sec2_new,

drivers/gpu/drm/nouveau/nvkm/engine/gr/tu102.c

+26 −0
Original line number Diff line number Diff line
@@ -164,6 +164,32 @@ MODULE_FIRMWARE("nvidia/tu106/gr/sw_nonctx.bin"); 
MODULE_FIRMWARE("nvidia/tu106/gr/sw_bundle_init.bin");

MODULE_FIRMWARE("nvidia/tu106/gr/sw_method_init.bin");



MODULE_FIRMWARE("nvidia/tu117/gr/fecs_bl.bin");

MODULE_FIRMWARE("nvidia/tu117/gr/fecs_inst.bin");

MODULE_FIRMWARE("nvidia/tu117/gr/fecs_data.bin");

MODULE_FIRMWARE("nvidia/tu117/gr/fecs_sig.bin");

MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_bl.bin");

MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_inst.bin");

MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_data.bin");

MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_sig.bin");

MODULE_FIRMWARE("nvidia/tu117/gr/sw_ctx.bin");

MODULE_FIRMWARE("nvidia/tu117/gr/sw_nonctx.bin");

MODULE_FIRMWARE("nvidia/tu117/gr/sw_bundle_init.bin");

MODULE_FIRMWARE("nvidia/tu117/gr/sw_method_init.bin");



MODULE_FIRMWARE("nvidia/tu116/gr/fecs_bl.bin");

MODULE_FIRMWARE("nvidia/tu116/gr/fecs_inst.bin");

MODULE_FIRMWARE("nvidia/tu116/gr/fecs_data.bin");

MODULE_FIRMWARE("nvidia/tu116/gr/fecs_sig.bin");

MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_bl.bin");

MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_inst.bin");

MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_data.bin");

MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_sig.bin");

MODULE_FIRMWARE("nvidia/tu116/gr/sw_ctx.bin");

MODULE_FIRMWARE("nvidia/tu116/gr/sw_nonctx.bin");

MODULE_FIRMWARE("nvidia/tu116/gr/sw_bundle_init.bin");

MODULE_FIRMWARE("nvidia/tu116/gr/sw_method_init.bin");



static const struct gf100_gr_fwif

tu102_gr_fwif[] = {

	{ 0, gm200_gr_load, &tu102_gr, &gp108_gr_fecs_acr, &gp108_gr_gpccs_acr },

drivers/gpu/drm/nouveau/nvkm/subdev/acr/tu102.c

+14 −0
Original line number Diff line number Diff line
@@ -107,6 +107,12 @@ MODULE_FIRMWARE("nvidia/tu104/acr/ucode_unload.bin"); 
MODULE_FIRMWARE("nvidia/tu106/acr/unload_bl.bin");

MODULE_FIRMWARE("nvidia/tu106/acr/ucode_unload.bin");



MODULE_FIRMWARE("nvidia/tu116/acr/unload_bl.bin");

MODULE_FIRMWARE("nvidia/tu116/acr/ucode_unload.bin");



MODULE_FIRMWARE("nvidia/tu117/acr/unload_bl.bin");

MODULE_FIRMWARE("nvidia/tu117/acr/ucode_unload.bin");



static const struct nvkm_acr_hsf_fwif

tu102_acr_unload_fwif[] = {

	{  0, nvkm_acr_hsfw_load, &gp108_acr_unload_0 },
@@ -130,6 +136,8 @@ tu102_acr_asb_0 = { 
MODULE_FIRMWARE("nvidia/tu102/acr/ucode_asb.bin");

MODULE_FIRMWARE("nvidia/tu104/acr/ucode_asb.bin");

MODULE_FIRMWARE("nvidia/tu106/acr/ucode_asb.bin");

MODULE_FIRMWARE("nvidia/tu116/acr/ucode_asb.bin");

MODULE_FIRMWARE("nvidia/tu117/acr/ucode_asb.bin");



static const struct nvkm_acr_hsf_fwif

tu102_acr_asb_fwif[] = {
@@ -154,6 +162,12 @@ MODULE_FIRMWARE("nvidia/tu104/acr/ucode_ahesasc.bin"); 
MODULE_FIRMWARE("nvidia/tu106/acr/bl.bin");

MODULE_FIRMWARE("nvidia/tu106/acr/ucode_ahesasc.bin");



MODULE_FIRMWARE("nvidia/tu116/acr/bl.bin");

MODULE_FIRMWARE("nvidia/tu116/acr/ucode_ahesasc.bin");



MODULE_FIRMWARE("nvidia/tu117/acr/bl.bin");

MODULE_FIRMWARE("nvidia/tu117/acr/ucode_ahesasc.bin");



static const struct nvkm_acr_hsf_fwif

tu102_acr_ahesasc_fwif[] = {

	{  0, nvkm_acr_hsfw_load, &tu102_acr_ahesasc_0 },

drivers/gpu/drm/nouveau/nvkm/subdev/fb/gv100.c

+2 −0
Original line number Diff line number Diff line
@@ -51,3 +51,5 @@ MODULE_FIRMWARE("nvidia/gv100/nvdec/scrubber.bin"); 
MODULE_FIRMWARE("nvidia/tu102/nvdec/scrubber.bin");

MODULE_FIRMWARE("nvidia/tu104/nvdec/scrubber.bin");

MODULE_FIRMWARE("nvidia/tu106/nvdec/scrubber.bin");

MODULE_FIRMWARE("nvidia/tu116/nvdec/scrubber.bin");

MODULE_FIRMWARE("nvidia/tu117/nvdec/scrubber.bin");

CRA Git | Maintained and supported by SUSTech CRA and CCSE