Commit 7c03d653 authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt Committed by Paul Mackerras
Browse files

powerpc/mm: Introduce MMU features 



We're soon running out of CPU features and I need to add some new
ones for various MMU related bits, so this patch separates the MMU
features from the CPU features.  I moved over the 32-bit MMU related
ones, added base features for MMU type families, but didn't move
over any 64-bit only feature yet.

Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: default avatarKumar Gala <galak@kernel.crashing.org>
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
parent 2ca8cf73

arch/powerpc/include/asm/cputable.h

+37 −48
Original line number Diff line number Diff line
@@ -82,6 +82,7 @@ struct cpu_spec { 
	char		*cpu_name;

	unsigned long	cpu_features;		/* Kernel features */

	unsigned int	cpu_user_features;	/* Userland features */

	unsigned int	mmu_features;		/* MMU features */



	/* cache line sizes */

	unsigned int	icache_bsize;
@@ -144,17 +145,14 @@ extern const char *powerpc_base_platform; 
#define CPU_FTR_USE_TB			ASM_CONST(0x0000000000000040)

#define CPU_FTR_L2CSR			ASM_CONST(0x0000000000000080)

#define CPU_FTR_601			ASM_CONST(0x0000000000000100)

#define CPU_FTR_HPTE_TABLE		ASM_CONST(0x0000000000000200)

#define CPU_FTR_CAN_NAP			ASM_CONST(0x0000000000000400)

#define CPU_FTR_L3CR			ASM_CONST(0x0000000000000800)

#define CPU_FTR_L3_DISABLE_NAP		ASM_CONST(0x0000000000001000)

#define CPU_FTR_NAP_DISABLE_L2_PR	ASM_CONST(0x0000000000002000)

#define CPU_FTR_DUAL_PLL_750FX		ASM_CONST(0x0000000000004000)

#define CPU_FTR_NO_DPM			ASM_CONST(0x0000000000008000)

#define CPU_FTR_HAS_HIGH_BATS		ASM_CONST(0x0000000000010000)

#define CPU_FTR_NEED_COHERENT		ASM_CONST(0x0000000000020000)

#define CPU_FTR_NO_BTIC			ASM_CONST(0x0000000000040000)

#define CPU_FTR_BIG_PHYS		ASM_CONST(0x0000000000080000)

#define CPU_FTR_NODSISRALIGN		ASM_CONST(0x0000000000100000)

#define CPU_FTR_PPC_LE			ASM_CONST(0x0000000000200000)

#define CPU_FTR_REAL_LE			ASM_CONST(0x0000000000400000)
@@ -266,107 +264,99 @@ extern const char *powerpc_base_platform; 
		     !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \

		     !defined(CONFIG_BOOKE))



#define CPU_FTRS_PPC601	(CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE | \

#define CPU_FTRS_PPC601	(CPU_FTR_COMMON | CPU_FTR_601 | \

	CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)

#define CPU_FTRS_603	(CPU_FTR_COMMON | \

	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)

#define CPU_FTRS_604	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_PPC_LE)

	    CPU_FTR_USE_TB | CPU_FTR_PPC_LE)

#define CPU_FTRS_740_NOTAU	(CPU_FTR_COMMON | \

	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \

	    CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)

#define CPU_FTRS_740	(CPU_FTR_COMMON | \

	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \

	    CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \

	    CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \

	    CPU_FTR_PPC_LE)

#define CPU_FTRS_750	(CPU_FTR_COMMON | \

	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \

	    CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \

	    CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \

	    CPU_FTR_PPC_LE)

#define CPU_FTRS_750CL	(CPU_FTRS_750 | CPU_FTR_HAS_HIGH_BATS)

#define CPU_FTRS_750CL	(CPU_FTRS_750)

#define CPU_FTRS_750FX1	(CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)

#define CPU_FTRS_750FX2	(CPU_FTRS_750 | CPU_FTR_NO_DPM)

#define CPU_FTRS_750FX	(CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | \

		CPU_FTR_HAS_HIGH_BATS)

#define CPU_FTRS_750FX	(CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)

#define CPU_FTRS_750GX	(CPU_FTRS_750FX)

#define CPU_FTRS_7400_NOTAU	(CPU_FTR_COMMON | \

	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \

	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \

	    CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)

#define CPU_FTRS_7400	(CPU_FTR_COMMON | \

	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \

	    CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \

	    CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)

#define CPU_FTRS_7450_20	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \

	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \

	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)

#define CPU_FTRS_7450_21	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \

	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \

	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \

	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)

#define CPU_FTRS_7450_23	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \

	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \

	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)

#define CPU_FTRS_7455_1	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \

	    CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \

	    CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \

	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)

	    CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)

#define CPU_FTRS_7455_20	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \

	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \

	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \

	    CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)

	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)

#define CPU_FTRS_7455	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \

	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \

	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \

	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)

#define CPU_FTRS_7447_10	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \

	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \

	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \

	    CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \

	    CPU_FTR_NEED_PAIRED_STWCX)

#define CPU_FTRS_7447	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \

	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \

	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \

	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)

#define CPU_FTRS_7447A	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \

	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \

	    CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \

	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)

#define CPU_FTRS_7448	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \

	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \

	    CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \

	    CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)

#define CPU_FTRS_82XX	(CPU_FTR_COMMON | \

	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)

#define CPU_FTRS_G2_LE	(CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \

	    CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS)

	    CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP)

#define CPU_FTRS_E300	(CPU_FTR_MAYBE_CAN_DOZE | \

	    CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \

	    CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \

	    CPU_FTR_COMMON)

#define CPU_FTRS_E300C2	(CPU_FTR_MAYBE_CAN_DOZE | \

	    CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \

	    CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \

	    CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)

#define CPU_FTRS_CLASSIC32	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)

#define CPU_FTRS_CLASSIC32	(CPU_FTR_COMMON | CPU_FTR_USE_TB)

#define CPU_FTRS_8XX	(CPU_FTR_USE_TB)

#define CPU_FTRS_40X	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)

#define CPU_FTRS_44X	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
@@ -379,55 +369,54 @@ extern const char *powerpc_base_platform; 
	    CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \

	    CPU_FTR_NOEXECUTE)

#define CPU_FTRS_E500_2	(CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \

	    CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | \

	    CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \

	    CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)

#define CPU_FTRS_E500MC	(CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \

	    CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE)

#define CPU_FTRS_GENERIC_32	(CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)



/* 64-bit CPUs */

#define CPU_FTRS_POWER3	(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

	    CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)

	    CPU_FTR_IABR | CPU_FTR_PPC_LE)

#define CPU_FTRS_RS64	(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

	    CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \

	    CPU_FTR_IABR | \

	    CPU_FTR_MMCRA | CPU_FTR_CTRL)

#define CPU_FTRS_POWER4	(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ)

#define CPU_FTRS_PPC970	(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \

	    CPU_FTR_CP_USE_DCBTZ)

#define CPU_FTRS_POWER5	(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_MMCRA | CPU_FTR_SMT | \

	    CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \

	    CPU_FTR_PURR)

#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_MMCRA | CPU_FTR_SMT | \

	    CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \

	    CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \

	    CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD)

#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_MMCRA | CPU_FTR_SMT | \

	    CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \

	    CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \

	    CPU_FTR_DSCR | CPU_FTR_SAO)

#define CPU_FTRS_CELL	(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \

	    CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | \

	    CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \

	    CPU_FTR_UNALIGNED_LD_STD)

#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \

	    CPU_FTR_PPCAS_ARCH_V2 | \

	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \

	    CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B)

#define CPU_FTRS_COMPATIBLE	(CPU_FTR_USE_TB | \

	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)

#define CPU_FTRS_COMPATIBLE	(CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)



#ifdef __powerpc64__

#define CPU_FTRS_POSSIBLE	\

arch/powerpc/include/asm/feature-fixups.h

+30 −0
Original line number Diff line number Diff line
@@ -81,6 +81,36 @@ label##5: \ 
#define ALT_FTR_SECTION_END_IFCLR(msk)	\

	ALT_FTR_SECTION_END_NESTED_IFCLR(msk, 97)



/* MMU feature dependent sections */

#define BEGIN_MMU_FTR_SECTION_NESTED(label)	START_FTR_SECTION(label)

#define BEGIN_MMU_FTR_SECTION			START_FTR_SECTION(97)



#define END_MMU_FTR_SECTION_NESTED(msk, val, label) 		\

	FTR_SECTION_ELSE_NESTED(label)				\

	MAKE_FTR_SECTION_ENTRY(msk, val, label, __mmu_ftr_fixup)



#define END_MMU_FTR_SECTION(msk, val)		\

	END_MMU_FTR_SECTION_NESTED(msk, val, 97)



#define END_MMU_FTR_SECTION_IFSET(msk)	END_MMU_FTR_SECTION((msk), (msk))

#define END_MMU_FTR_SECTION_IFCLR(msk)	END_MMU_FTR_SECTION((msk), 0)



/* MMU feature sections with alternatives, use BEGIN_FTR_SECTION to start */

#define MMU_FTR_SECTION_ELSE_NESTED(label)	FTR_SECTION_ELSE_NESTED(label)

#define MMU_FTR_SECTION_ELSE	MMU_FTR_SECTION_ELSE_NESTED(97)

#define ALT_MMU_FTR_SECTION_END_NESTED(msk, val, label)	\

	MAKE_FTR_SECTION_ENTRY(msk, val, label, __mmu_ftr_fixup)

#define ALT_MMU_FTR_SECTION_END_NESTED_IFSET(msk, label)	\

	ALT_MMU_FTR_SECTION_END_NESTED(msk, msk, label)

#define ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(msk, label)	\

	ALT_MMU_FTR_SECTION_END_NESTED(msk, 0, label)

#define ALT_MMU_FTR_SECTION_END(msk, val)	\

	ALT_MMU_FTR_SECTION_END_NESTED(msk, val, 97)

#define ALT_MMU_FTR_SECTION_END_IFSET(msk)	\

	ALT_MMU_FTR_SECTION_END_NESTED_IFSET(msk, 97)

#define ALT_MMU_FTR_SECTION_END_IFCLR(msk)	\

	ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(msk, 97)



/* Firmware feature dependent sections */

#define BEGIN_FW_FTR_SECTION_NESTED(label)	START_FTR_SECTION(label)

#define BEGIN_FW_FTR_SECTION			START_FTR_SECTION(97)

arch/powerpc/include/asm/mmu.h

+41 −0
Original line number Diff line number Diff line
@@ -2,6 +2,47 @@ 
#define _ASM_POWERPC_MMU_H_

#ifdef __KERNEL__



#include <asm/asm-compat.h>

#include <asm/feature-fixups.h>



/*

 * MMU features bit definitions

 */



/*

 * First half is MMU families

 */

#define MMU_FTR_HPTE_TABLE		ASM_CONST(0x00000001)

#define MMU_FTR_TYPE_8xx		ASM_CONST(0x00000002)

#define MMU_FTR_TYPE_40x		ASM_CONST(0x00000004)

#define MMU_FTR_TYPE_44x		ASM_CONST(0x00000008)

#define MMU_FTR_TYPE_FSL_E		ASM_CONST(0x00000010)



/*

 * This is individual features

 */



/* Enable use of high BAT registers */

#define MMU_FTR_USE_HIGH_BATS		ASM_CONST(0x00010000)



/* Enable >32-bit physical addresses on 32-bit processor, only used

 * by CONFIG_6xx currently as BookE supports that from day 1

 */

#define MMU_FTR_BIG_PHYS		ASM_CONST(0x00020000)



#ifndef __ASSEMBLY__

#include <asm/cputable.h>



static inline int mmu_has_feature(unsigned long feature)

{

	return (cur_cpu_spec->mmu_features & feature);

}



extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;



#endif /* !__ASSEMBLY__ */





#ifdef CONFIG_PPC64

/* 64-bit classic hash table MMU */

#  include <asm/mmu-hash64.h>

arch/powerpc/kernel/cputable.c

+113 −0

File changed.

Preview size limit exceeded, changes collapsed.

arch/powerpc/kernel/head_32.S

+4 −4
Original line number Diff line number Diff line
@@ -990,12 +990,12 @@ load_up_mmu: 
	LOAD_BAT(1,r3,r4,r5)

	LOAD_BAT(2,r3,r4,r5)

	LOAD_BAT(3,r3,r4,r5)

BEGIN_FTR_SECTION

BEGIN_MMU_FTR_SECTION

	LOAD_BAT(4,r3,r4,r5)

	LOAD_BAT(5,r3,r4,r5)

	LOAD_BAT(6,r3,r4,r5)

	LOAD_BAT(7,r3,r4,r5)

END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS)

END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)

	blr



/*
@@ -1141,7 +1141,7 @@ clear_bats: 
	mtspr	SPRN_IBAT2L,r10

	mtspr	SPRN_IBAT3U,r10

	mtspr	SPRN_IBAT3L,r10

BEGIN_FTR_SECTION

BEGIN_MMU_FTR_SECTION

	/* Here's a tweak: at this point, CPU setup have

	 * not been called yet, so HIGH_BAT_EN may not be

	 * set in HID0 for the 745x processors. However, it
@@ -1164,7 +1164,7 @@ BEGIN_FTR_SECTION 
	mtspr	SPRN_IBAT6L,r10

	mtspr	SPRN_IBAT7U,r10

	mtspr	SPRN_IBAT7L,r10

END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS)

END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)

	blr



flush_tlbs:

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