Commit 7c019191 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'xtensa-20150830' of git://github.com/czankel/xtensa-linux 

Pull xtensa updates from Chris Zankel:
 "Xtensa fixes and improvements for 4.3:

   - reimplement DMA API using common helpers
   - implement counting and sampling perf events using hardware perf
     counters
   - add fake NMI support for hardware perf counters
   - fix THREADPTR register reloading on return to userspace
   - keep exception/interrupt stack continuous for debugger
   - improve vmlinux.lds.S post-processing"

* tag 'xtensa-20150830' of git://github.com/czankel/xtensa-linux:
  xtensa: improve vmlinux.lds.S sed post-processing
  xtensa: drop unused irq_err_count
  xtensa: implement fake NMI
  xtensa: don't touch EXC_TABLE_FIXUP in _switch_to
  xtensa: fix kernel register spilling
  xtensa: reorganize irq flags tracing
  perf tools: xtensa: add DWARF register names
  xtensa: implement counting and sampling perf events
  xtensa: count software page fault perf events
  xtensa: add profiling IRQ type to xtensa_irq_map
  xtensa: select PERF_USE_VMALLOC for cache-aliasing configurations
  xtensa: move oprofile stack tracing to stacktrace.c
  xtensa: keep exception/interrupt stack continuous
  xtensa: clean up Kconfig dependencies for custom cores
  xtensa: reimplement DMA API using common helpers
  xtensa: fix threadptr reload on return to userspace
  xtensa: ISS: add missing va_end into split_if_spec
parents 7b8067d3 650c9197

arch/xtensa/Kconfig

+16 −8
Original line number Diff line number Diff line
@@ -14,12 +14,15 @@ config XTENSA 
	select GENERIC_IRQ_SHOW

	select GENERIC_PCI_IOMAP

	select GENERIC_SCHED_CLOCK

	select HAVE_DMA_API_DEBUG

	select HAVE_DMA_ATTRS

	select HAVE_FUNCTION_TRACER

	select HAVE_IRQ_TIME_ACCOUNTING

	select HAVE_OPROFILE

	select HAVE_PERF_EVENTS

	select IRQ_DOMAIN

	select MODULES_USE_ELF_RELA

	select PERF_USE_VMALLOC

	select VIRT_TO_BUS

	help

	  Xtensa processors are 32-bit RISC machines designed by Tensilica
@@ -61,9 +64,7 @@ config TRACE_IRQFLAGS_SUPPORT 
	def_bool y



config MMU

	bool

	default n if !XTENSA_VARIANT_CUSTOM

	default XTENSA_VARIANT_MMU if XTENSA_VARIANT_CUSTOM

	def_bool n



config VARIANT_IRQ_SWITCH

	def_bool n
@@ -71,9 +72,6 @@ config VARIANT_IRQ_SWITCH 
config HAVE_XTENSA_GPIO32

	def_bool n



config MAY_HAVE_SMP

	def_bool n



menu "Processor type and features"



choice
@@ -100,7 +98,6 @@ config XTENSA_VARIANT_DC233C 


config XTENSA_VARIANT_CUSTOM

	bool "Custom Xtensa processor configuration"

	select MAY_HAVE_SMP

	select HAVE_XTENSA_GPIO32

	help

	  Select this variant to use a custom Xtensa processor configuration.
@@ -126,10 +123,21 @@ config XTENSA_VARIANT_MMU 
	bool "Core variant has a Full MMU (TLB, Pages, Protection, etc)"

	depends on XTENSA_VARIANT_CUSTOM

	default y

	select MMU

	help

	  Build a Conventional Kernel with full MMU support,

	  ie: it supports a TLB with auto-loading, page protection.



config XTENSA_VARIANT_HAVE_PERF_EVENTS

	bool "Core variant has Performance Monitor Module"

	depends on XTENSA_VARIANT_CUSTOM

	default n

	help

	  Enable if core variant has Performance Monitor Module with

	  External Registers Interface.



	  If unsure, say N.



config XTENSA_UNALIGNED_USER

	bool "Unaligned memory access in use space"

	help
@@ -143,7 +151,7 @@ source "kernel/Kconfig.preempt" 


config HAVE_SMP

	bool "System Supports SMP (MX)"

	depends on MAY_HAVE_SMP

	depends on XTENSA_VARIANT_CUSTOM

	select XTENSA_MX

	help

	  This option is use to indicate that the system-on-a-chip (SOC)

arch/xtensa/include/asm/Kbuild

+0 −1
Original line number Diff line number Diff line
@@ -2,7 +2,6 @@ generic-y += bitsperlong.h 
generic-y += bug.h

generic-y += clkdev.h

generic-y += cputime.h

generic-y += device.h

generic-y += div64.h

generic-y += emergency-restart.h

generic-y += errno.h

arch/xtensa/include/asm/atomic.h

+5 −5
Original line number Diff line number Diff line
@@ -29,7 +29,7 @@ 
 *

 * Locking interrupts looks like this:

 *

 *    rsil a15, LOCKLEVEL

 *    rsil a15, TOPLEVEL

 *    <code>

 *    wsr  a15, PS

 *    rsync
@@ -106,7 +106,7 @@ static inline void atomic_##op(int i, atomic_t * v) \ 
	unsigned int vval;						\

									\

	__asm__ __volatile__(						\

			"       rsil    a15, "__stringify(LOCKLEVEL)"\n"\

			"       rsil    a15, "__stringify(TOPLEVEL)"\n"\

			"       l32i    %0, %2, 0\n"			\

			"       " #op " %0, %0, %1\n"			\

			"       s32i    %0, %2, 0\n"			\
@@ -124,7 +124,7 @@ static inline int atomic_##op##_return(int i, atomic_t * v) \ 
	unsigned int vval;						\

									\

	__asm__ __volatile__(						\

			"       rsil    a15,"__stringify(LOCKLEVEL)"\n"	\

			"       rsil    a15,"__stringify(TOPLEVEL)"\n"	\

			"       l32i    %0, %2, 0\n"			\

			"       " #op " %0, %0, %1\n"			\

			"       s32i    %0, %2, 0\n"			\
@@ -272,7 +272,7 @@ static inline void atomic_clear_mask(unsigned int mask, atomic_t *v) 
	unsigned int vval;



	__asm__ __volatile__(

			"       rsil    a15,"__stringify(LOCKLEVEL)"\n"

			"       rsil    a15,"__stringify(TOPLEVEL)"\n"

			"       l32i    %0, %2, 0\n"

			"       xor     %1, %4, %3\n"

			"       and     %0, %0, %4\n"
@@ -306,7 +306,7 @@ static inline void atomic_set_mask(unsigned int mask, atomic_t *v) 
	unsigned int vval;



	__asm__ __volatile__(

			"       rsil    a15,"__stringify(LOCKLEVEL)"\n"

			"       rsil    a15,"__stringify(TOPLEVEL)"\n"

			"       l32i    %0, %2, 0\n"

			"       or      %0, %0, %1\n"

			"       s32i    %0, %2, 0\n"

arch/xtensa/include/asm/cmpxchg.h

+2 −2
Original line number Diff line number Diff line
@@ -34,7 +34,7 @@ __cmpxchg_u32(volatile int *p, int old, int new) 
	return new;

#else

	__asm__ __volatile__(

			"       rsil    a15, "__stringify(LOCKLEVEL)"\n"

			"       rsil    a15, "__stringify(TOPLEVEL)"\n"

			"       l32i    %0, %1, 0\n"

			"       bne     %0, %2, 1f\n"

			"       s32i    %3, %1, 0\n"
@@ -123,7 +123,7 @@ static inline unsigned long xchg_u32(volatile int * m, unsigned long val) 
#else

	unsigned long tmp;

	__asm__ __volatile__(

			"       rsil    a15, "__stringify(LOCKLEVEL)"\n"

			"       rsil    a15, "__stringify(TOPLEVEL)"\n"

			"       l32i    %0, %1, 0\n"

			"       s32i    %2, %1, 0\n"

			"       wsr     a15, ps\n"

arch/xtensa/include/asm/device.h

0 → 100644
+19 −0
Original line number Diff line number Diff line 
/*

 * Arch specific extensions to struct device

 *

 * This file is released under the GPLv2

 */

#ifndef _ASM_XTENSA_DEVICE_H

#define _ASM_XTENSA_DEVICE_H



struct dma_map_ops;



struct dev_archdata {

	/* DMA operations on that device */

	struct dma_map_ops *dma_ops;

};



struct pdev_archdata {

};



#endif /* _ASM_XTENSA_DEVICE_H */

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