drm/amd/display: Add the DMUB service (7c008829) · Commits · 戴 / test

drivers/gpu/drm/amd/display/Kconfig

+6 −0

Original line number	Diff line number	Diff line
		@@ -30,6 +30,7 @@ config DRM_AMD_DC_DCN2_1
		bool "DCN 2.1 family"
		depends on DRM_AMD_DC && X86
		depends on DRM_AMD_DC_DCN2_0
		select DRM_AMD_DC_DMUB
		help
		Choose this option if you want to have
		Renoir support for display engine
		@@ -52,6 +53,11 @@ config DRM_AMD_DC_HDCP
		if you want to support
		HDCP authentication

		config DRM_AMD_DC_DMUB
		def_bool n
		help
		DMUB support for display engine

		config DEBUG_KERNEL_DC
		bool "Enable kgdb break in DC"
		depends on DRM_AMD_DC

drivers/gpu/drm/amd/display/Makefile

+8 −0

Original line number	Diff line number	Diff line
		@@ -38,6 +38,10 @@ ifdef CONFIG_DRM_AMD_DC_HDCP
		subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/hdcp
		endif

		ifdef CONFIG_DRM_AMD_DC_DMUB
		subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dmub/inc
		endif

		#TODO: remove when Timing Sync feature is complete
		subdir-ccflags-y += -DBUILD_FEATURE_TIMING_SYNC=0

		@@ -47,6 +51,10 @@ ifdef CONFIG_DRM_AMD_DC_HDCP
		DAL_LIBS += modules/hdcp
		endif

		ifdef CONFIG_DRM_AMD_DC_DMUB
		DAL_LIBS += dmub/src
		endif

		AMD_DAL = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DISPLAY_PATH)/,$(DAL_LIBS)))

		include $(AMD_DAL)

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

0 → 100644

+256 −0

Original line number	Diff line number	Diff line
		/*
		* Copyright 2019 Advanced Micro Devices, Inc.
		*
		* Permission is hereby granted, free of charge, to any person obtaining a
		* copy of this software and associated documentation files (the "Software"),
		* to deal in the Software without restriction, including without limitation
		* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		* and/or sell copies of the Software, and to permit persons to whom the
		* Software is furnished to do so, subject to the following conditions:
		*
		* The above copyright notice and this permission notice shall be included in
		* all copies or substantial portions of the Software.
		*
		* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		* OTHER DEALINGS IN THE SOFTWARE.
		*
		* Authors: AMD
		*
		*/

		#ifndef _DMUB_CMD_H_
		#define _DMUB_CMD_H_

		#include "dmub_types.h"
		#include "atomfirmware.h"

		#define DMUB_RB_CMD_SIZE 64
		#define DMUB_RB_MAX_ENTRY 128
		#define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY)
		#define REG_SET_MASK 0xFFFF

		enum dmub_cmd_type {
		DMUB_CMD__NULL,
		DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE,
		DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ,
		DMUB_CMD__REG_SEQ_BURST_WRITE,
		DMUB_CMD__REG_REG_WAIT,
		DMUB_CMD__DIGX_ENCODER_CONTROL,
		DMUB_CMD__SET_PIXEL_CLOCK,
		DMUB_CMD__ENABLE_DISP_POWER_GATING,
		DMUB_CMD__DPPHY_INIT,
		DMUB_CMD__DIG1_TRANSMITTER_CONTROL,

		// PSR
		DMUB_CMD__PSR_ENABLE,
		DMUB_CMD__PSR_DISABLE,
		DMUB_CMD__PSR_COPY_SETTINGS,
		DMUB_CMD__PSR_SET_LEVEL,
		};

		#pragma pack(push, 1)

		struct dmub_cmd_header {
		enum dmub_cmd_type type : 8;
		unsigned int reserved0 : 16;
		unsigned int payload_bytes : 6; /* up to 60 bytes */
		unsigned int reserved : 2;
		};

		/*
		* Read modify write
		*
		* 60 payload bytes can hold up to 5 sets of read modify writes,
		* each take 3 dwords.
		*
		* number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence)
		*
		* modify_mask = 0xffff'ffff means all fields are going to be updated. in this case
		* command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write
		*/
		struct dmub_cmd_read_modify_write_sequence {
		uint32_t addr;
		uint32_t modify_mask;
		uint32_t modify_value;
		};

		#define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5
		struct dmub_rb_cmd_read_modify_write {
		struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE
		struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX];
		};

		/*
		* Update a register with specified masks and values sequeunce
		*
		* 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword
		*
		* number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence)
		*
		*
		* USE CASE:
		* 1. auto-increment register where additional read would update pointer and produce wrong result
		* 2. toggle a bit without read in the middle
		*/

		struct dmub_cmd_reg_field_update_sequence {
		uint32_t modify_mask; // 0xffff'ffff to skip initial read
		uint32_t modify_value;
		};

		#define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7

		struct dmub_rb_cmd_reg_field_update_sequence {
		struct dmub_cmd_header header;
		uint32_t addr;
		struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX];
		};


		/*
		* Burst write
		*
		* support use case such as writing out LUTs.
		*
		* 60 payload bytes can hold up to 14 values to write to given address
		*
		* number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence)
		*/
		#define DMUB_BURST_WRITE_VALUES__MAX 14
		struct dmub_rb_cmd_burst_write {
		struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_BURST_WRITE
		uint32_t addr;
		uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX];
		};


		struct dmub_rb_cmd_common {
		struct dmub_cmd_header header;
		uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)];
		};

		struct dmub_cmd_reg_wait_data {
		uint32_t addr;
		uint32_t mask;
		uint32_t condition_field_value;
		uint32_t time_out_us;
		};

		struct dmub_rb_cmd_reg_wait {
		struct dmub_cmd_header header;
		struct dmub_cmd_reg_wait_data reg_wait;
		};

		struct dmub_cmd_digx_encoder_control_data {
		union dig_encoder_control_parameters_v1_5 dig;
		};

		struct dmub_rb_cmd_digx_encoder_control {
		struct dmub_cmd_header header;
		struct dmub_cmd_digx_encoder_control_data encoder_control;
		};

		struct dmub_cmd_set_pixel_clock_data {
		struct set_pixel_clock_parameter_v1_7 clk;
		};

		struct dmub_rb_cmd_set_pixel_clock {
		struct dmub_cmd_header header;
		struct dmub_cmd_set_pixel_clock_data pixel_clock;
		};

		struct dmub_cmd_enable_disp_power_gating_data {
		struct enable_disp_power_gating_parameters_v2_1 pwr;
		};

		struct dmub_rb_cmd_enable_disp_power_gating {
		struct dmub_cmd_header header;
		struct dmub_cmd_enable_disp_power_gating_data power_gating;
		};

		struct dmub_cmd_dig1_transmitter_control_data {
		struct dig_transmitter_control_parameters_v1_6 dig;
		};

		struct dmub_rb_cmd_dig1_transmitter_control {
		struct dmub_cmd_header header;
		struct dmub_cmd_dig1_transmitter_control_data transmitter_control;
		};

		struct dmub_rb_cmd_dpphy_init {
		struct dmub_cmd_header header;
		uint8_t reserved[60];
		};

		struct dmub_cmd_psr_copy_settings_data {
		uint32_t reg1;
		uint32_t reg2;
		uint32_t reg3;
		};

		struct dmub_rb_cmd_psr_copy_settings {
		struct dmub_cmd_header header;
		struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data;
		};

		struct dmub_cmd_psr_set_level_data {
		uint16_t psr_level;
		};

		struct dmub_rb_cmd_psr_set_level {
		struct dmub_cmd_header header;
		struct dmub_cmd_psr_set_level_data psr_set_level_data;
		};

		struct dmub_rb_cmd_psr_disable {
		struct dmub_cmd_header header;
		};

		struct dmub_rb_cmd_psr_enable {
		struct dmub_cmd_header header;
		};

		struct dmub_cmd_psr_notify_vblank_data {
		uint32_t vblank_int; // Which vblank interrupt was triggered
		};

		struct dmub_rb_cmd_notify_vblank {
		struct dmub_cmd_header header;
		struct dmub_cmd_psr_notify_vblank_data psr_notify_vblank_data;
		};

		struct dmub_cmd_psr_notify_static_state_data {
		uint32_t ss_int; // Which static screen interrupt was triggered
		uint32_t ss_enter; // Enter (1) or exit (0) static screen
		};

		struct dmub_rb_cmd_psr_notify_static_state {
		struct dmub_cmd_header header;
		struct dmub_cmd_psr_notify_static_state_data psr_notify_static_state_data;
		};

		union dmub_rb_cmd {
		struct dmub_rb_cmd_read_modify_write read_modify_write;
		struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq;
		struct dmub_rb_cmd_burst_write burst_write;
		struct dmub_rb_cmd_reg_wait reg_wait;
		struct dmub_rb_cmd_common cmd_common;
		struct dmub_rb_cmd_digx_encoder_control digx_encoder_control;
		struct dmub_rb_cmd_set_pixel_clock set_pixel_clock;
		struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating;
		struct dmub_rb_cmd_dpphy_init dpphy_init;
		struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control;
		struct dmub_rb_cmd_psr_enable psr_enable;
		struct dmub_rb_cmd_psr_disable psr_disable;
		struct dmub_rb_cmd_psr_copy_settings psr_copy_settings;
		struct dmub_rb_cmd_psr_set_level psr_set_level;
		};

		#pragma pack(pop)

		#endif /* _DMUB_CMD_H_ */

drivers/gpu/drm/amd/display/dmub/inc/dmub_rb.h

0 → 100644

+129 −0

Original line number	Diff line number	Diff line
		/*
		* Copyright 2019 Advanced Micro Devices, Inc.
		*
		* Permission is hereby granted, free of charge, to any person obtaining a
		* copy of this software and associated documentation files (the "Software"),
		* to deal in the Software without restriction, including without limitation
		* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		* and/or sell copies of the Software, and to permit persons to whom the
		* Software is furnished to do so, subject to the following conditions:
		*
		* The above copyright notice and this permission notice shall be included in
		* all copies or substantial portions of the Software.
		*
		* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		* OTHER DEALINGS IN THE SOFTWARE.
		*
		* Authors: AMD
		*
		*/

		#ifndef _DMUB_RB_H_
		#define _DMUB_RB_H_

		#include "dmub_types.h"
		#include "dmub_cmd.h"

		#if defined(__cplusplus)
		extern "C" {
		#endif

		struct dmub_cmd_header;

		struct dmub_rb_init_params {
		void *ctx;
		void *base_address;
		uint32_t capacity;
		};

		struct dmub_rb {
		void *base_address;
		uint32_t data_count;
		uint32_t rptr;
		uint32_t wrpt;
		uint32_t capacity;

		void *ctx;
		void *dmub;
		};


		static inline bool dmub_rb_empty(struct dmub_rb *rb)
		{
		return (rb->wrpt == rb->rptr);
		}

		static inline bool dmub_rb_full(struct dmub_rb *rb)
		{
		uint32_t data_count;

		if (rb->wrpt >= rb->rptr)
		data_count = rb->wrpt - rb->rptr;
		else
		data_count = rb->capacity - (rb->rptr - rb->wrpt);

		return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE));
		}

		static inline bool dmub_rb_push_front(struct dmub_rb *rb,
		const struct dmub_cmd_header *cmd)
		{
		uint8_t wt_ptr = (uint8_t )(rb->base_address) + rb->wrpt;

		if (dmub_rb_full(rb))
		return false;

		dmub_memcpy(wt_ptr, cmd, DMUB_RB_CMD_SIZE);
		rb->wrpt += DMUB_RB_CMD_SIZE;

		if (rb->wrpt >= rb->capacity)
		rb->wrpt %= rb->capacity;

		return true;
		}

		static inline bool dmub_rb_front(struct dmub_rb *rb,
		struct dmub_cmd_header *cmd)
		{
		uint8_t rd_ptr = (uint8_t )rb->base_address + rb->rptr;

		if (dmub_rb_empty(rb))
		return false;

		dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE);

		return true;
		}

		static inline bool dmub_rb_pop_front(struct dmub_rb *rb)
		{
		if (dmub_rb_empty(rb))
		return false;

		rb->rptr += DMUB_RB_CMD_SIZE;

		if (rb->rptr >= rb->capacity)
		rb->rptr %= rb->capacity;

		return true;
		}

		static inline void dmub_rb_init(struct dmub_rb *rb,
		struct dmub_rb_init_params *init_params)
		{
		rb->base_address = init_params->base_address;
		rb->capacity = init_params->capacity;
		rb->rptr = 0;
		rb->wrpt = 0;
		}

		#if defined(__cplusplus)
		}
		#endif

		#endif /* _DMUB_RB_H_ */

drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h

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+505 −0

File added.

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