clk: sunxi-ng: h3/h5: Fix CSI_MCLK parent (7bb7d29c) · Commits · 戴 / test

The third parent of CSI_MCLK is PLL_PERIPH1, not PLL_PERIPH0. Fix it. Fixes: ("clk: sunxi-ng: Add H3 clocks") Acked-by:

drivers/clk/sunxi-ng/ccu-sun8i-h3.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -476,7 +476,7 @@ static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
		static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
		0x134, 16, 4, 24, 3, BIT(31), 0);

		static const char * const csi_mclk_parents[] = { "osc24M", "pll-video", "pll-periph0" };
		static const char * const csi_mclk_parents[] = { "osc24M", "pll-video", "pll-periph1" };
		static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents,
		0x134, 0, 5, 8, 3, BIT(15), 0);