Commit 7b9c7e30 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
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drm/amd/pm: drop unnecessary wrappers around watermark setting 



The convertion to "struct dm_pp_clock_range_for_mcif_wm_set_soc15"
is totally unnecessary and can be dropped.

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Tested-by: default avatarChangfeng Zhu <Changfeng.Zhu@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 12684c66

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

+2 −95
Original line number Diff line number Diff line
@@ -664,49 +664,8 @@ static enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp, 
{

	const struct dc_context *ctx = pp->dm;

	struct amdgpu_device *adev = ctx->driver_context;

	struct dm_pp_wm_sets_with_clock_ranges_soc15 wm_with_clock_ranges;

	struct dm_pp_clock_range_for_dmif_wm_set_soc15 *wm_dce_clocks =

			wm_with_clock_ranges.wm_dmif_clocks_ranges;

	struct dm_pp_clock_range_for_mcif_wm_set_soc15 *wm_soc_clocks =

			wm_with_clock_ranges.wm_mcif_clocks_ranges;

	int32_t i;



	wm_with_clock_ranges.num_wm_dmif_sets = ranges->num_reader_wm_sets;

	wm_with_clock_ranges.num_wm_mcif_sets = ranges->num_writer_wm_sets;



	for (i = 0; i < wm_with_clock_ranges.num_wm_dmif_sets; i++) {

		if (ranges->reader_wm_sets[i].wm_inst > 3)

			wm_dce_clocks[i].wm_set_id = WM_SET_A;

		else

			wm_dce_clocks[i].wm_set_id =

					ranges->reader_wm_sets[i].wm_inst;

		wm_dce_clocks[i].wm_max_dcfclk_clk_in_khz =

			ranges->reader_wm_sets[i].max_drain_clk_mhz * 1000;

		wm_dce_clocks[i].wm_min_dcfclk_clk_in_khz =

			ranges->reader_wm_sets[i].min_drain_clk_mhz * 1000;

		wm_dce_clocks[i].wm_max_mem_clk_in_khz =

			ranges->reader_wm_sets[i].max_fill_clk_mhz * 1000;

		wm_dce_clocks[i].wm_min_mem_clk_in_khz =

			ranges->reader_wm_sets[i].min_fill_clk_mhz * 1000;

	}



	for (i = 0; i < wm_with_clock_ranges.num_wm_mcif_sets; i++) {

		if (ranges->writer_wm_sets[i].wm_inst > 3)

			wm_soc_clocks[i].wm_set_id = WM_SET_A;

		else

			wm_soc_clocks[i].wm_set_id =

					ranges->writer_wm_sets[i].wm_inst;

		wm_soc_clocks[i].wm_max_socclk_clk_in_khz =

			ranges->writer_wm_sets[i].max_fill_clk_mhz * 1000;

		wm_soc_clocks[i].wm_min_socclk_clk_in_khz =

			ranges->writer_wm_sets[i].min_fill_clk_mhz * 1000;

		wm_soc_clocks[i].wm_max_mem_clk_in_khz =

			ranges->writer_wm_sets[i].max_drain_clk_mhz * 1000;

		wm_soc_clocks[i].wm_min_mem_clk_in_khz =

			ranges->writer_wm_sets[i].min_drain_clk_mhz * 1000;

	}



	smu_set_watermarks_for_clock_ranges(&adev->smu,	&wm_with_clock_ranges);

	smu_set_watermarks_for_clock_ranges(&adev->smu, ranges);



	return PP_SMU_RESULT_OK;

}
@@ -917,60 +876,8 @@ static enum pp_smu_status pp_rn_set_wm_ranges(struct pp_smu *pp, 
{

	const struct dc_context *ctx = pp->dm;

	struct amdgpu_device *adev = ctx->driver_context;

	struct smu_context *smu = &adev->smu;

	struct dm_pp_wm_sets_with_clock_ranges_soc15 wm_with_clock_ranges;

	struct dm_pp_clock_range_for_dmif_wm_set_soc15 *wm_dce_clocks =

			wm_with_clock_ranges.wm_dmif_clocks_ranges;

	struct dm_pp_clock_range_for_mcif_wm_set_soc15 *wm_soc_clocks =

			wm_with_clock_ranges.wm_mcif_clocks_ranges;

	int32_t i;



	if (!smu->ppt_funcs)

		return PP_SMU_RESULT_UNSUPPORTED;



	wm_with_clock_ranges.num_wm_dmif_sets = ranges->num_reader_wm_sets;

	wm_with_clock_ranges.num_wm_mcif_sets = ranges->num_writer_wm_sets;



	for (i = 0; i < wm_with_clock_ranges.num_wm_dmif_sets; i++) {

		if (ranges->reader_wm_sets[i].wm_inst > 3)

			wm_dce_clocks[i].wm_set_id = WM_SET_A;

		else

			wm_dce_clocks[i].wm_set_id =

					ranges->reader_wm_sets[i].wm_inst;



		wm_dce_clocks[i].wm_min_dcfclk_clk_in_khz =

			ranges->reader_wm_sets[i].min_drain_clk_mhz;



		wm_dce_clocks[i].wm_max_dcfclk_clk_in_khz =

			ranges->reader_wm_sets[i].max_drain_clk_mhz;



		wm_dce_clocks[i].wm_min_mem_clk_in_khz =

			ranges->reader_wm_sets[i].min_fill_clk_mhz;



		wm_dce_clocks[i].wm_max_mem_clk_in_khz =

			ranges->reader_wm_sets[i].max_fill_clk_mhz;

	}



	for (i = 0; i < wm_with_clock_ranges.num_wm_mcif_sets; i++) {

		if (ranges->writer_wm_sets[i].wm_inst > 3)

			wm_soc_clocks[i].wm_set_id = WM_SET_A;

		else

			wm_soc_clocks[i].wm_set_id =

					ranges->writer_wm_sets[i].wm_inst;

		wm_soc_clocks[i].wm_min_socclk_clk_in_khz =

				ranges->writer_wm_sets[i].min_fill_clk_mhz;



		wm_soc_clocks[i].wm_max_socclk_clk_in_khz =

			ranges->writer_wm_sets[i].max_fill_clk_mhz;



		wm_soc_clocks[i].wm_min_mem_clk_in_khz =

			ranges->writer_wm_sets[i].min_drain_clk_mhz;



		wm_soc_clocks[i].wm_max_mem_clk_in_khz =

			ranges->writer_wm_sets[i].max_drain_clk_mhz;

	}



	smu_set_watermarks_for_clock_ranges(&adev->smu, &wm_with_clock_ranges);

	smu_set_watermarks_for_clock_ranges(&adev->smu, ranges);



	return PP_SMU_RESULT_OK;

}

drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h

+2 −2
Original line number Diff line number Diff line
@@ -501,7 +501,7 @@ struct pptable_funcs { 
	bool (*is_dpm_running)(struct smu_context *smu);

	int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed);

	int (*set_watermarks_table)(struct smu_context *smu,

				    struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);

				    struct pp_smu_wm_range_sets *clock_ranges);

	int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range);

	int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states);

	int (*set_default_od_settings)(struct smu_context *smu);
@@ -755,7 +755,7 @@ enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu); 
int smu_write_watermarks_table(struct smu_context *smu);

int smu_set_watermarks_for_clock_ranges(

		struct smu_context *smu,

		struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);

		struct pp_smu_wm_range_sets *clock_ranges);



/* smu to display interface */

extern int smu_display_configuration_change(struct smu_context *smu, const

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

+1 −1
Original line number Diff line number Diff line
@@ -1828,7 +1828,7 @@ int smu_write_watermarks_table(struct smu_context *smu) 
}



int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,

		struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)

		struct pp_smu_wm_range_sets *clock_ranges)

{

	int ret = 0;

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

+27 −41
Original line number Diff line number Diff line
@@ -1589,57 +1589,43 @@ static int navi10_notify_smc_display_config(struct smu_context *smu) 
}



static int navi10_set_watermarks_table(struct smu_context *smu,

				       struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)

				       struct pp_smu_wm_range_sets *clock_ranges)

{

	Watermarks_t *table = smu->smu_table.watermarks_table;

	int ret = 0;

	int i;



	if (clock_ranges) {

		if (clock_ranges->num_wm_dmif_sets > 4 ||

		    clock_ranges->num_wm_mcif_sets > 4)

		if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||

		    clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)

			return -EINVAL;



		for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {

			table->WatermarkRow[1][i].MinClock =

				cpu_to_le16((uint16_t)

				(clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /

				1000));

			table->WatermarkRow[1][i].MaxClock =

				cpu_to_le16((uint16_t)

				(clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /

				1000));

			table->WatermarkRow[1][i].MinUclk =

				cpu_to_le16((uint16_t)

				(clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /

				1000));

			table->WatermarkRow[1][i].MaxUclk =

				cpu_to_le16((uint16_t)

				(clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /

				1000));

			table->WatermarkRow[1][i].WmSetting = (uint8_t)

					clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;

		}



		for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {

			table->WatermarkRow[0][i].MinClock =

				cpu_to_le16((uint16_t)

				(clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /

				1000));

			table->WatermarkRow[0][i].MaxClock =

				cpu_to_le16((uint16_t)

				(clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /

				1000));

			table->WatermarkRow[0][i].MinUclk =

				cpu_to_le16((uint16_t)

				(clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /

				1000));

			table->WatermarkRow[0][i].MaxUclk =

				cpu_to_le16((uint16_t)

				(clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /

				1000));

			table->WatermarkRow[0][i].WmSetting = (uint8_t)

					clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;

		for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {

			table->WatermarkRow[WM_DCEFCLK][i].MinClock =

				clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;

			table->WatermarkRow[WM_DCEFCLK][i].MaxClock =

				clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;

			table->WatermarkRow[WM_DCEFCLK][i].MinUclk =

				clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;

			table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =

				clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;



			table->WatermarkRow[WM_DCEFCLK][i].WmSetting =

				clock_ranges->reader_wm_sets[i].wm_inst;

		}



		for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {

			table->WatermarkRow[WM_SOCCLK][i].MinClock =

				clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;

			table->WatermarkRow[WM_SOCCLK][i].MaxClock =

				clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;

			table->WatermarkRow[WM_SOCCLK][i].MinUclk =

				clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;

			table->WatermarkRow[WM_SOCCLK][i].MaxUclk =

				clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;



			table->WatermarkRow[WM_SOCCLK][i].WmSetting =

				clock_ranges->writer_wm_sets[i].wm_inst;

		}



		smu->watermarks_bitmap |= WATERMARKS_EXIST;

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

+27 −42
Original line number Diff line number Diff line
@@ -1407,58 +1407,43 @@ static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu) 
}



static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,

					       struct dm_pp_wm_sets_with_clock_ranges_soc15

					       *clock_ranges)

					       struct pp_smu_wm_range_sets *clock_ranges)

{

	Watermarks_t *table = smu->smu_table.watermarks_table;

	int ret = 0;

	int i;



	if (clock_ranges) {

		if (clock_ranges->num_wm_dmif_sets > 4 ||

		    clock_ranges->num_wm_mcif_sets > 4)

		if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||

		    clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)

			return -EINVAL;



		for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {

			table->WatermarkRow[1][i].MinClock =

				cpu_to_le16((uint16_t)

				(clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /

				1000));

			table->WatermarkRow[1][i].MaxClock =

				cpu_to_le16((uint16_t)

				(clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /

				1000));

			table->WatermarkRow[1][i].MinUclk =

				cpu_to_le16((uint16_t)

				(clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /

				1000));

			table->WatermarkRow[1][i].MaxUclk =

				cpu_to_le16((uint16_t)

				(clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /

				1000));

			table->WatermarkRow[1][i].WmSetting = (uint8_t)

					clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;

		}



		for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {

			table->WatermarkRow[0][i].MinClock =

				cpu_to_le16((uint16_t)

				(clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /

				1000));

			table->WatermarkRow[0][i].MaxClock =

				cpu_to_le16((uint16_t)

				(clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /

				1000));

			table->WatermarkRow[0][i].MinUclk =

				cpu_to_le16((uint16_t)

				(clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /

				1000));

			table->WatermarkRow[0][i].MaxUclk =

				cpu_to_le16((uint16_t)

				(clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /

				1000));

			table->WatermarkRow[0][i].WmSetting = (uint8_t)

					clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;

		for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {

			table->WatermarkRow[WM_DCEFCLK][i].MinClock =

				clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;

			table->WatermarkRow[WM_DCEFCLK][i].MaxClock =

				clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;

			table->WatermarkRow[WM_DCEFCLK][i].MinUclk =

				clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;

			table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =

				clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;



			table->WatermarkRow[WM_DCEFCLK][i].WmSetting =

				clock_ranges->reader_wm_sets[i].wm_inst;

		}



		for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {

			table->WatermarkRow[WM_SOCCLK][i].MinClock =

				clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;

			table->WatermarkRow[WM_SOCCLK][i].MaxClock =

				clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;

			table->WatermarkRow[WM_SOCCLK][i].MinUclk =

				clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;

			table->WatermarkRow[WM_SOCCLK][i].MaxUclk =

				clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;



			table->WatermarkRow[WM_SOCCLK][i].WmSetting =

				clock_ranges->writer_wm_sets[i].wm_inst;

		}



		smu->watermarks_bitmap |= WATERMARKS_EXIST;

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