Commit 7b6e4ea0 authored by Omer Shpigelman's avatar Omer Shpigelman Committed by Oded Gabbay
Browse files

habanalabs: type specific MMU cache invalidation 



Add the ability to invalidate the necessary MMU cache only.
This ability is a prerequisite for future ASICs support.
Note that in Goya ASIC, a single cache is used for both host/DRAM
mappings and hence this patch should not have any effect on current
behavior.

Signed-off-by: default avatarOmer Shpigelman <oshpigelman@habana.ai>
Reviewed-by: default avatarOded Gabbay <oded.gabbay@gmail.com>
Signed-off-by: default avatarOded Gabbay <oded.gabbay@gmail.com>
parent 7f74d4d3

drivers/misc/habanalabs/goya/goya.c

+4 −2
Original line number Diff line number Diff line
@@ -2463,7 +2463,8 @@ int goya_mmu_init(struct hl_device *hdev) 
	WREG32_AND(mmSTLB_STLB_FEATURE_EN,

			(~STLB_STLB_FEATURE_EN_FOLLOWER_EN_MASK));



	hdev->asic_funcs->mmu_invalidate_cache(hdev, true);

	hdev->asic_funcs->mmu_invalidate_cache(hdev, true,

					VM_TYPE_USERPTR | VM_TYPE_PHYS_PACK);



	WREG32(mmMMU_MMU_ENABLE, 1);

	WREG32(mmMMU_SPI_MASK, 0xF);
@@ -4845,7 +4846,8 @@ static void goya_mmu_prepare(struct hl_device *hdev, u32 asid) 
		goya_mmu_prepare_reg(hdev, goya_mmu_regs[i], asid);

}



static void goya_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard)

static void goya_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard,

					u32 flags)

{

	struct goya_device *goya = hdev->asic_specific;

	u32 status, timeout_usec;

drivers/misc/habanalabs/habanalabs.h

+6 −5
Original line number Diff line number Diff line
@@ -114,8 +114,8 @@ struct hw_queue_properties { 
 * @VM_TYPE_PHYS_PACK: mapping of DRAM memory to device virtual address.

 */

enum vm_type_t {

	VM_TYPE_USERPTR,

	VM_TYPE_PHYS_PACK

	VM_TYPE_USERPTR = 0x1,

	VM_TYPE_PHYS_PACK = 0x2

};



/**
@@ -483,8 +483,8 @@ enum hl_pll_frequency { 
 * @get_events_stat: retrieve event queue entries histogram.

 * @read_pte: read MMU page table entry from DRAM.

 * @write_pte: write MMU page table entry to DRAM.

 * @mmu_invalidate_cache: flush MMU STLB cache, either with soft (L1 only) or

 *                        hard (L0 & L1) flush.

 * @mmu_invalidate_cache: flush MMU STLB host/DRAM cache, either with soft

 *                        (L1 only) or hard (L0 & L1) flush.

 * @mmu_invalidate_cache_range: flush specific MMU STLB cache lines with

 *                              ASID-VA-size mask.

 * @send_heartbeat: send is-alive packet to ArmCP and verify response.
@@ -565,7 +565,8 @@ struct hl_asic_funcs { 
				u32 *size);

	u64 (*read_pte)(struct hl_device *hdev, u64 addr);

	void (*write_pte)(struct hl_device *hdev, u64 addr, u64 val);

	void (*mmu_invalidate_cache)(struct hl_device *hdev, bool is_hard);

	void (*mmu_invalidate_cache)(struct hl_device *hdev, bool is_hard,

					u32 flags);

	void (*mmu_invalidate_cache_range)(struct hl_device *hdev, bool is_hard,

			u32 asid, u64 va, u64 size);

	int (*send_heartbeat)(struct hl_device *hdev);

drivers/misc/habanalabs/memory.c

+2 −2
Original line number Diff line number Diff line
@@ -944,7 +944,7 @@ static int map_device_va(struct hl_ctx *ctx, struct hl_mem_in *args, 
		goto map_err;

	}



	hdev->asic_funcs->mmu_invalidate_cache(hdev, false);

	hdev->asic_funcs->mmu_invalidate_cache(hdev, false, *vm_type);



	mutex_unlock(&ctx->mmu_lock);
@@ -1060,7 +1060,7 @@ static int unmap_device_va(struct hl_ctx *ctx, u64 vaddr) 


	unmap_phys_pg_pack(ctx, vaddr, phys_pg_pack);



	hdev->asic_funcs->mmu_invalidate_cache(hdev, true);

	hdev->asic_funcs->mmu_invalidate_cache(hdev, true, *vm_type);



	mutex_unlock(&ctx->mmu_lock);

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