Commit 7b56caf3 authored by Madhav Chauhan's avatar Madhav Chauhan Committed by Jani Nikula
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drm/i915/icl: Define DSI transcoder timing registers 



This patch defines registers and bitfields used for
programming DSI transcoder's horizontal and vertical
timings.

v2: Remove TRANS_TIMING_SHIFT definition

v3 by Jani:
 - Group macros by transcoder

Signed-off-by: default avatarMadhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/dcc329280e3aca5b4fc3482c5bcaa0cac043c5d8.1539613303.git.jani.nikula@intel.com
parent 70f4f502

drivers/gpu/drm/i915/i915_reg.h

+14 −0
Original line number Diff line number Diff line
@@ -4023,6 +4023,20 @@ enum { 
#define _VSYNCSHIFT_B	0x61028

#define _PIPE_MULT_B	0x6102c



/* DSI 0 timing regs */

#define _HTOTAL_DSI0		0x6b000

#define _HSYNC_DSI0		0x6b008

#define _VTOTAL_DSI0		0x6b00c

#define _VSYNC_DSI0		0x6b014

#define _VSYNCSHIFT_DSI0	0x6b028



/* DSI 1 timing regs */

#define _HTOTAL_DSI1		0x6b800

#define _HSYNC_DSI1		0x6b808

#define _VTOTAL_DSI1		0x6b80c

#define _VSYNC_DSI1		0x6b814

#define _VSYNCSHIFT_DSI1	0x6b828



#define TRANSCODER_A_OFFSET 0x60000

#define TRANSCODER_B_OFFSET 0x61000

#define TRANSCODER_C_OFFSET 0x62000

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