drm/i915: Add whitelist workarounds for ICL (7b3d4063) · Commits · 戴 / test

Updated whitelist table for ICL. v2: Reduce changes to just those required for media driver until the selftest can be updated to support the new features of the other entries. Signed-off-by:

John Harrison <John.C.Harrison@Intel.com> Signed-off-by:

Robert M. Fosha <robert.m.fosha@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by:

Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by:

Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190618010108.27499-4-John.C.Harrison@Intel.com

drivers/gpu/drm/i915/gt/intel_workarounds.c

+27 −11

Original line number	Diff line number	Diff line
		@@ -1113,9 +1113,8 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)
		{
		struct i915_wa_list *w = &engine->whitelist;

		if (engine->class != RENDER_CLASS)
		return;

		switch (engine->class) {
		case RENDER_CLASS:
		/* WaAllowUMDToModifyHalfSliceChicken7:icl */
		whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);

		@@ -1124,6 +1123,23 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)

		/* WaEnableStateCacheRedirectToCS:icl */
		whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
		break;

		case VIDEO_DECODE_CLASS:
		/* hucStatusRegOffset */
		whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base),
		RING_FORCE_TO_NONPRIV_RD);
		/* hucUKernelHdrInfoRegOffset */
		whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base),
		RING_FORCE_TO_NONPRIV_RD);
		/* hucStatus2RegOffset */
		whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base),
		RING_FORCE_TO_NONPRIV_RD);
		break;

		default:
		break;
		}
		}

		void intel_engine_init_whitelist(struct intel_engine_cs *engine)

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