Commit 7b286af3 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus 

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
  [MIPS] Ensure that ST0_FR is never set on a 32 bit kernel
  [MIPS] time: Delete weak definition of plat_time_init() due to gcc bug.
  [MIPS] PCI: Make pcibios_fixup_device_resources ignore legacy resources.
  [MIPS] Atlas, Malta: Don't free firmware memory on free_initmem.
  [MIPS] Alchemy: fix off by two error in __fixup_bigphys_addr()
  [MIPS] Alchemy: fix PCI resource conflict
  [MIPS] time: Set up Cobalt's mips_hpt_frequency
parents 6e301393 bbaf238b

arch/mips/au1000/Kconfig

+0 −9
Original line number Diff line number Diff line
@@ -7,7 +7,6 @@ config MIPS_MTX1 
	bool "4G Systems MTX-1 board"

	select DMA_NONCOHERENT

	select HW_HAS_PCI

	select RESOURCES_64BIT if PCI

	select SOC_AU1500

	select SYS_SUPPORTS_LITTLE_ENDIAN
@@ -22,7 +21,6 @@ config MIPS_DB1000 
	select SOC_AU1000

	select DMA_NONCOHERENT

	select HW_HAS_PCI

	select RESOURCES_64BIT if PCI

	select SYS_SUPPORTS_LITTLE_ENDIAN



config MIPS_DB1100
@@ -44,7 +42,6 @@ config MIPS_DB1500 
	select DMA_NONCOHERENT

	select HW_HAS_PCI

	select MIPS_DISABLE_OBSOLETE_IDE

	select RESOURCES_64BIT if PCI

	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_SUPPORTS_LITTLE_ENDIAN
@@ -54,7 +51,6 @@ config MIPS_DB1550 
	select HW_HAS_PCI

	select DMA_NONCOHERENT

	select MIPS_DISABLE_OBSOLETE_IDE

	select RESOURCES_64BIT if PCI

	select SYS_SUPPORTS_LITTLE_ENDIAN



config MIPS_MIRAGE
@@ -68,7 +64,6 @@ config MIPS_PB1000 
	select SOC_AU1000

	select DMA_NONCOHERENT

	select HW_HAS_PCI

	select RESOURCES_64BIT if PCI

	select SWAP_IO_SPACE

	select SYS_SUPPORTS_LITTLE_ENDIAN
@@ -77,7 +72,6 @@ config MIPS_PB1100 
	select SOC_AU1100

	select DMA_NONCOHERENT

	select HW_HAS_PCI

	select RESOURCES_64BIT if PCI

	select SWAP_IO_SPACE

	select SYS_SUPPORTS_LITTLE_ENDIAN
@@ -86,7 +80,6 @@ config MIPS_PB1200 
	select SOC_AU1200

	select DMA_NONCOHERENT

	select MIPS_DISABLE_OBSOLETE_IDE

	select RESOURCES_64BIT if PCI

	select SYS_SUPPORTS_LITTLE_ENDIAN



config MIPS_PB1500
@@ -94,7 +87,6 @@ config MIPS_PB1500 
	select SOC_AU1500

	select DMA_NONCOHERENT

	select HW_HAS_PCI

	select RESOURCES_64BIT if PCI

	select SYS_SUPPORTS_LITTLE_ENDIAN



config MIPS_PB1550
@@ -103,7 +95,6 @@ config MIPS_PB1550 
	select DMA_NONCOHERENT

	select HW_HAS_PCI

	select MIPS_DISABLE_OBSOLETE_IDE

	select RESOURCES_64BIT if PCI

	select SYS_SUPPORTS_LITTLE_ENDIAN



config MIPS_XXS1500

arch/mips/au1000/common/pci.c

+4 −4
Original line number Diff line number Diff line
@@ -39,15 +39,15 @@ 


/* TBD */

static struct resource pci_io_resource = {

	.start	= (resource_size_t)PCI_IO_START,

	.end	= (resource_size_t)PCI_IO_END,

	.start	= PCI_IO_START,

	.end	= PCI_IO_END,

	.name	= "PCI IO space",

	.flags	= IORESOURCE_IO

};



static struct resource pci_mem_resource = {

	.start	= (resource_size_t)PCI_MEM_START,

	.end	= (resource_size_t)PCI_MEM_END,

	.start	= PCI_MEM_START,

	.end	= PCI_MEM_END,

	.name	= "PCI memory space",

	.flags	= IORESOURCE_MEM

};

arch/mips/au1000/common/setup.c

+4 −5
Original line number Diff line number Diff line
@@ -137,12 +137,11 @@ phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size) 


#ifdef CONFIG_PCI

	{

		u32 start, end;

		u32 start = (u32)Au1500_PCI_MEM_START;

		u32 end   = (u32)Au1500_PCI_MEM_END;



		start = (u32)Au1500_PCI_MEM_START;

		end = (u32)Au1500_PCI_MEM_END;

		/* check for pci memory window */

		if ((phys_addr >= start) && ((phys_addr + size) < end))

		/* Check for PCI memory window */

		if (phys_addr >= start && (phys_addr + size - 1) <= end)

			return (phys_t)

			       ((phys_addr - start) + Au1500_PCI_MEM_START);

	}

arch/mips/cobalt/time.c

+20 −1
Original line number Diff line number Diff line
@@ -27,9 +27,28 @@ 


void __init plat_time_init(void)

{

	u32 start, end;

	int i = HZ / 10;



	setup_pit_timer();



	gt641xx_set_base_clock(GT641XX_BASE_CLOCK);



	mips_timer_state = gt641xx_timer0_state;

	/*

	 * MIPS counter frequency is measured during a 100msec interval

	 * using GT64111 timer0.

	 */

	while (!gt641xx_timer0_state())

		;



	start = read_c0_count();



	while (i--)

		while (!gt641xx_timer0_state())

			;



	end = read_c0_count();



	mips_hpt_frequency = (end - start) * 10;

	printk(KERN_INFO "MIPS counter frequency %dHz\n", mips_hpt_frequency);

}

arch/mips/kernel/process.c

+1 −2
Original line number Diff line number Diff line
@@ -77,9 +77,8 @@ void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp) 
	unsigned long status;



	/* New thread loses kernel privileges. */

	status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|KU_MASK);

	status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|ST0_FR|KU_MASK);

#ifdef CONFIG_64BIT

	status &= ~ST0_FR;

	status |= test_thread_flag(TIF_32BIT_REGS) ? 0 : ST0_FR;

#endif

	status |= KU_USER;

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