Commit 7b174c5e authored by Jerome Brunet's avatar Jerome Brunet Committed by Neil Armstrong
Browse files

clk: meson: remove obsolete comments 



Over time things changes in CCF and issues have been fixed in meson
controllers.

Now, clk81 is decently modeled by read-only PLLs, a mux, a divider
and a gate. We can remove the FIXME comments related to clk81.
Also remove the comment about devm_clk_hw_register, as there is
apparently nothing wrong with it.

Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
parent 14bd7b9c

drivers/clk/meson/axg.c

+0 −5
Original line number Diff line number Diff line
@@ -411,11 +411,6 @@ static struct meson_clk_mpll axg_mpll3 = { 
	},

};



/*

 * FIXME The legacy composite clocks (e.g. clk81) are both PLL post-dividers

 * and should be modeled with their respective PLLs via the forthcoming

 * coordinated clock rates feature

 */

static u32 mux_table_clk81[]	= { 0, 2, 3, 4, 5, 6, 7 };

static const char * const clk81_parent_names[] = {

	"xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",

drivers/clk/meson/gxbb.c

+0 −6
Original line number Diff line number Diff line
@@ -575,12 +575,6 @@ static struct meson_clk_mpll gxbb_mpll2 = { 
	},

};



/*

 * FIXME The legacy composite clocks (e.g. clk81) are both PLL post-dividers

 * and should be modeled with their respective PLLs via the forthcoming

 * coordinated clock rates feature

 */



static u32 mux_table_clk81[]	= { 0, 2, 3, 4, 5, 6, 7 };

static const char * const clk81_parent_names[] = {

	"xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",

drivers/clk/meson/meson8b.c

+0 −1
Original line number Diff line number Diff line
@@ -849,7 +849,6 @@ static int meson8b_clkc_probe(struct platform_device *pdev) 
		if (!meson8b_hw_onecell_data.hws[i])

			continue;



		/* FIXME convert to devm_clk_register */

		ret = devm_clk_hw_register(dev, meson8b_hw_onecell_data.hws[i]);

		if (ret)

			return ret;

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