crypto: qat - Intel(R) QAT DH895xcc accelerator (7afa232e) · Commits · 戴 / test

drivers/crypto/qat/qat_dh895xcc/Makefile

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		ccflags-y := -I$(CURDIR)/drivers/crypto/qat/qat_common
		obj-$(CONFIG_CRYPTO_DEV_QAT_DH895xCC) += qat_dh895xcc.o
		qat_dh895xcc-objs := adf_drv.o \
		adf_isr.o \
		adf_dh895xcc_hw_data.o \
		adf_hw_arbiter.o \
		qat_admin.o \
		adf_admin.o

drivers/crypto/qat/qat_dh895xcc/adf_admin.c

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		/*
		This file is provided under a dual BSD/GPLv2 license. When using or
		redistributing this file, you may do so under either license.

		GPL LICENSE SUMMARY
		Copyright(c) 2014 Intel Corporation.
		This program is free software; you can redistribute it and/or modify
		it under the terms of version 2 of the GNU General Public License as
		published by the Free Software Foundation.

		This program is distributed in the hope that it will be useful, but
		WITHOUT ANY WARRANTY; without even the implied warranty of
		MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
		General Public License for more details.

		Contact Information:
		qat-linux@intel.com

		BSD LICENSE
		Copyright(c) 2014 Intel Corporation.
		Redistribution and use in source and binary forms, with or without
		modification, are permitted provided that the following conditions
		are met:

		* Redistributions of source code must retain the above copyright
		notice, this list of conditions and the following disclaimer.
		* Redistributions in binary form must reproduce the above copyright
		notice, this list of conditions and the following disclaimer in
		the documentation and/or other materials provided with the
		distribution.
		* Neither the name of Intel Corporation nor the names of its
		contributors may be used to endorse or promote products derived
		from this software without specific prior written permission.

		THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
		"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
		LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
		A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
		OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
		SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
		LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
		DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
		THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
		(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
		OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
		*/
		#include <linux/types.h>
		#include <linux/mutex.h>
		#include <linux/slab.h>
		#include <linux/delay.h>
		#include <linux/pci.h>
		#include <linux/dma-mapping.h>
		#include <adf_accel_devices.h>
		#include "adf_drv.h"
		#include "adf_dh895xcc_hw_data.h"

		#define ADF_ADMINMSG_LEN 32

		struct adf_admin_comms {
		dma_addr_t phy_addr;
		void *virt_addr;
		void __iomem *mailbox_addr;
		struct mutex lock; /* protects adf_admin_comms struct */
		};

		int adf_put_admin_msg_sync(struct adf_accel_dev *accel_dev,
		uint32_t ae, void in, void out)
		{
		struct adf_admin_comms *admin = accel_dev->admin;
		int offset = ae * ADF_ADMINMSG_LEN * 2;
		void __iomem *mailbox = admin->mailbox_addr;
		int mb_offset = ae * ADF_DH895XCC_MAILBOX_STRIDE;
		int times, received;

		mutex_lock(&admin->lock);

		if (ADF_CSR_RD(mailbox, mb_offset) == 1) {
		mutex_unlock(&admin->lock);
		return -EAGAIN;
		}

		memcpy(admin->virt_addr + offset, in, ADF_ADMINMSG_LEN);
		ADF_CSR_WR(mailbox, mb_offset, 1);
		received = 0;
		for (times = 0; times < 50; times++) {
		msleep(20);
		if (ADF_CSR_RD(mailbox, mb_offset) == 0) {
		received = 1;
		break;
		}
		}
		if (received)
		memcpy(out, admin->virt_addr + offset +
		ADF_ADMINMSG_LEN, ADF_ADMINMSG_LEN);
		else
		pr_err("QAT: Failed to send admin msg to accelerator\n");

		mutex_unlock(&admin->lock);
		return received ? 0 : -EFAULT;
		}

		int adf_init_admin_comms(struct adf_accel_dev *accel_dev)
		{
		struct adf_admin_comms *admin;
		struct adf_bar *pmisc = &GET_BARS(accel_dev)[ADF_DH895XCC_PMISC_BAR];
		void __iomem *csr = pmisc->virt_addr;
		void __iomem *mailbox = csr + ADF_DH895XCC_MAILBOX_BASE_OFFSET;
		uint64_t reg_val;

		admin = kzalloc_node(sizeof(*accel_dev->admin), GFP_KERNEL,
		accel_dev->numa_node);
		if (!admin)
		return -ENOMEM;
		admin->virt_addr = dma_zalloc_coherent(&GET_DEV(accel_dev), PAGE_SIZE,
		&admin->phy_addr, GFP_KERNEL);
		if (!admin->virt_addr) {
		dev_err(&GET_DEV(accel_dev), "Failed to allocate dma buff\n");
		kfree(admin);
		return -ENOMEM;
		}
		reg_val = (uint64_t)admin->phy_addr;
		ADF_CSR_WR(csr, ADF_DH895XCC_ADMINMSGUR_OFFSET, reg_val >> 32);
		ADF_CSR_WR(csr, ADF_DH895XCC_ADMINMSGLR_OFFSET, reg_val);
		mutex_init(&admin->lock);
		admin->mailbox_addr = mailbox;
		accel_dev->admin = admin;
		return 0;
		}

		void adf_exit_admin_comms(struct adf_accel_dev *accel_dev)
		{
		struct adf_admin_comms *admin = accel_dev->admin;

		if (!admin)
		return;

		if (admin->virt_addr)
		dma_free_coherent(&GET_DEV(accel_dev), PAGE_SIZE,
		admin->virt_addr, admin->phy_addr);

		mutex_destroy(&admin->lock);
		kfree(admin);
		accel_dev->admin = NULL;
		}

drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

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		/*
		This file is provided under a dual BSD/GPLv2 license. When using or
		redistributing this file, you may do so under either license.

		GPL LICENSE SUMMARY
		Copyright(c) 2014 Intel Corporation.
		This program is free software; you can redistribute it and/or modify
		it under the terms of version 2 of the GNU General Public License as
		published by the Free Software Foundation.

		This program is distributed in the hope that it will be useful, but
		WITHOUT ANY WARRANTY; without even the implied warranty of
		MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
		General Public License for more details.

		Contact Information:
		qat-linux@intel.com

		BSD LICENSE
		Copyright(c) 2014 Intel Corporation.
		Redistribution and use in source and binary forms, with or without
		modification, are permitted provided that the following conditions
		are met:

		* Redistributions of source code must retain the above copyright
		notice, this list of conditions and the following disclaimer.
		* Redistributions in binary form must reproduce the above copyright
		notice, this list of conditions and the following disclaimer in
		the documentation and/or other materials provided with the
		distribution.
		* Neither the name of Intel Corporation nor the names of its
		contributors may be used to endorse or promote products derived
		from this software without specific prior written permission.

		THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
		"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
		LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
		A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
		OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
		SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
		LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
		DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
		THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
		(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
		OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
		*/
		#include <adf_accel_devices.h>
		#include "adf_dh895xcc_hw_data.h"
		#include "adf_drv.h"

		/* Worker thread to service arbiter mappings based on dev SKUs */
		static const uint32_t thrd_to_arb_map_sku4[] = {
		0x12222AAA, 0x11666666, 0x12222AAA, 0x11666666,
		0x12222AAA, 0x11222222, 0x12222AAA, 0x11222222,
		0x00000000, 0x00000000, 0x00000000, 0x00000000
		};

		static const uint32_t thrd_to_arb_map_sku6[] = {
		0x12222AAA, 0x11666666, 0x12222AAA, 0x11666666,
		0x12222AAA, 0x11222222, 0x12222AAA, 0x11222222,
		0x12222AAA, 0x11222222, 0x12222AAA, 0x11222222
		};

		static struct adf_hw_device_class dh895xcc_class = {
		.name = ADF_DH895XCC_DEVICE_NAME,
		.type = DEV_DH895XCC,
		.instances = 0
		};

		static uint32_t get_accel_mask(uint32_t fuse)
		{
		return (~fuse) >> ADF_DH895XCC_ACCELERATORS_REG_OFFSET &
		ADF_DH895XCC_ACCELERATORS_MASK;
		}

		static uint32_t get_ae_mask(uint32_t fuse)
		{
		return (~fuse) & ADF_DH895XCC_ACCELENGINES_MASK;
		}

		static uint32_t get_num_accels(struct adf_hw_device_data *self)
		{
		uint32_t i, ctr = 0;

		if (!self \|\| !self->accel_mask)
		return 0;

		for (i = 0; i < ADF_DH895XCC_MAX_ACCELERATORS; i++) {
		if (self->accel_mask & (1 << i))
		ctr++;
		}
		return ctr;
		}

		static uint32_t get_num_aes(struct adf_hw_device_data *self)
		{
		uint32_t i, ctr = 0;

		if (!self \|\| !self->ae_mask)
		return 0;

		for (i = 0; i < ADF_DH895XCC_MAX_ACCELENGINES; i++) {
		if (self->ae_mask & (1 << i))
		ctr++;
		}
		return ctr;
		}

		static uint32_t get_misc_bar_id(struct adf_hw_device_data *self)
		{
		return ADF_DH895XCC_PMISC_BAR;
		}

		static uint32_t get_etr_bar_id(struct adf_hw_device_data *self)
		{
		return ADF_DH895XCC_ETR_BAR;
		}

		static enum dev_sku_info get_sku(struct adf_hw_device_data *self)
		{
		int sku = (self->fuses & ADF_DH895XCC_FUSECTL_SKU_MASK)
		>> ADF_DH895XCC_FUSECTL_SKU_SHIFT;

		switch (sku) {
		case ADF_DH895XCC_FUSECTL_SKU_1:
		return DEV_SKU_1;
		case ADF_DH895XCC_FUSECTL_SKU_2:
		return DEV_SKU_2;
		case ADF_DH895XCC_FUSECTL_SKU_3:
		return DEV_SKU_3;
		case ADF_DH895XCC_FUSECTL_SKU_4:
		return DEV_SKU_4;
		default:
		return DEV_SKU_UNKNOWN;
		}
		return DEV_SKU_UNKNOWN;
		}

		void adf_get_arbiter_mapping(struct adf_accel_dev *accel_dev,
		uint32_t const **arb_map_config)
		{
		switch (accel_dev->accel_pci_dev.sku) {
		case DEV_SKU_1:
		*arb_map_config = thrd_to_arb_map_sku4;
		break;

		case DEV_SKU_2:
		case DEV_SKU_4:
		*arb_map_config = thrd_to_arb_map_sku6;
		break;
		default:
		pr_err("QAT: The configuration doesn't match any SKU");
		*arb_map_config = NULL;
		}
		}

		static void adf_enable_error_correction(struct adf_accel_dev *accel_dev)
		{
		struct adf_hw_device_data *hw_device = accel_dev->hw_device;
		struct adf_bar *misc_bar = &GET_BARS(accel_dev)[ADF_DH895XCC_PMISC_BAR];
		void __iomem *csr = misc_bar->virt_addr;
		unsigned int val, i;

		/* Enable Accel Engine error detection & correction */
		for (i = 0; i < hw_device->get_num_aes(hw_device); i++) {
		val = ADF_CSR_RD(csr, ADF_DH895XCC_AE_CTX_ENABLES(i));
		val \|= ADF_DH895XCC_ENABLE_AE_ECC_ERR;
		ADF_CSR_WR(csr, ADF_DH895XCC_AE_CTX_ENABLES(i), val);
		val = ADF_CSR_RD(csr, ADF_DH895XCC_AE_MISC_CONTROL(i));
		val \|= ADF_DH895XCC_ENABLE_AE_ECC_PARITY_CORR;
		ADF_CSR_WR(csr, ADF_DH895XCC_AE_MISC_CONTROL(i), val);
		}

		/* Enable shared memory error detection & correction */
		for (i = 0; i < hw_device->get_num_accels(hw_device); i++) {
		val = ADF_CSR_RD(csr, ADF_DH895XCC_UERRSSMSH(i));
		val \|= ADF_DH895XCC_ERRSSMSH_EN;
		ADF_CSR_WR(csr, ADF_DH895XCC_UERRSSMSH(i), val);
		val = ADF_CSR_RD(csr, ADF_DH895XCC_CERRSSMSH(i));
		val \|= ADF_DH895XCC_ERRSSMSH_EN;
		ADF_CSR_WR(csr, ADF_DH895XCC_CERRSSMSH(i), val);
		}
		}

		void adf_init_hw_data_dh895xcc(struct adf_hw_device_data *hw_data)
		{
		hw_data->dev_class = &dh895xcc_class;
		hw_data->instance_id = dh895xcc_class.instances++;
		hw_data->num_banks = ADF_DH895XCC_ETR_MAX_BANKS;
		hw_data->num_accel = ADF_DH895XCC_MAX_ACCELERATORS;
		hw_data->pci_dev_id = ADF_DH895XCC_PCI_DEVICE_ID;
		hw_data->num_logical_accel = 1;
		hw_data->num_engines = ADF_DH895XCC_MAX_ACCELENGINES;
		hw_data->tx_rx_gap = ADF_DH895XCC_RX_RINGS_OFFSET;
		hw_data->tx_rings_mask = ADF_DH895XCC_TX_RINGS_MASK;
		hw_data->alloc_irq = adf_isr_resource_alloc;
		hw_data->free_irq = adf_isr_resource_free;
		hw_data->enable_error_correction = adf_enable_error_correction;
		hw_data->hw_arb_ring_enable = adf_update_ring_arb_enable;
		hw_data->hw_arb_ring_disable = adf_update_ring_arb_enable;
		hw_data->get_accel_mask = get_accel_mask;
		hw_data->get_ae_mask = get_ae_mask;
		hw_data->get_num_accels = get_num_accels;
		hw_data->get_num_aes = get_num_aes;
		hw_data->get_etr_bar_id = get_etr_bar_id;
		hw_data->get_misc_bar_id = get_misc_bar_id;
		hw_data->get_sku = get_sku;
		hw_data->fw_name = ADF_DH895XCC_FW;
		}

		void adf_clean_hw_data_dh895xcc(struct adf_hw_device_data *hw_data)
		{
		hw_data->dev_class->instances--;
		}

drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.h

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		/*
		This file is provided under a dual BSD/GPLv2 license. When using or
		redistributing this file, you may do so under either license.

		GPL LICENSE SUMMARY
		Copyright(c) 2014 Intel Corporation.
		This program is free software; you can redistribute it and/or modify
		it under the terms of version 2 of the GNU General Public License as
		published by the Free Software Foundation.

		This program is distributed in the hope that it will be useful, but
		WITHOUT ANY WARRANTY; without even the implied warranty of
		MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
		General Public License for more details.

		Contact Information:
		qat-linux@intel.com

		BSD LICENSE
		Copyright(c) 2014 Intel Corporation.
		Redistribution and use in source and binary forms, with or without
		modification, are permitted provided that the following conditions
		are met:

		* Redistributions of source code must retain the above copyright
		notice, this list of conditions and the following disclaimer.
		* Redistributions in binary form must reproduce the above copyright
		notice, this list of conditions and the following disclaimer in
		the documentation and/or other materials provided with the
		distribution.
		* Neither the name of Intel Corporation nor the names of its
		contributors may be used to endorse or promote products derived
		from this software without specific prior written permission.

		THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
		"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
		LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
		A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
		OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
		SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
		LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
		DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
		THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
		(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
		OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
		*/
		#ifndef ADF_DH895x_HW_DATA_H_
		#define ADF_DH895x_HW_DATA_H_

		/* PCIe configuration space */
		#define ADF_DH895XCC_RX_RINGS_OFFSET 8
		#define ADF_DH895XCC_TX_RINGS_MASK 0xFF
		#define ADF_DH895XCC_FUSECTL_OFFSET 0x40
		#define ADF_DH895XCC_FUSECTL_SKU_MASK 0x300000
		#define ADF_DH895XCC_FUSECTL_SKU_SHIFT 20
		#define ADF_DH895XCC_FUSECTL_SKU_1 0x0
		#define ADF_DH895XCC_FUSECTL_SKU_2 0x1
		#define ADF_DH895XCC_FUSECTL_SKU_3 0x2
		#define ADF_DH895XCC_FUSECTL_SKU_4 0x3
		#define ADF_DH895XCC_MAX_ACCELERATORS 6
		#define ADF_DH895XCC_MAX_ACCELENGINES 12
		#define ADF_DH895XCC_ACCELERATORS_REG_OFFSET 18
		#define ADF_DH895XCC_ACCELERATORS_MASK 0x3F
		#define ADF_DH895XCC_ACCELENGINES_MASK 0xFFF
		#define ADF_DH895XCC_LEGFUSE_OFFSET 0x4C
		#define ADF_DH895XCC_ETR_MAX_BANKS 32
		#define ADF_DH895XCC_SMIAPF0_MASK_OFFSET (0x3A000 + 0x28)
		#define ADF_DH895XCC_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30)
		#define ADF_DH895XCC_SMIA0_MASK 0xFFFF
		#define ADF_DH895XCC_SMIA1_MASK 0x1
		/* Error detection and correction */
		#define ADF_DH895XCC_AE_CTX_ENABLES(i) (i * 0x1000 + 0x20818)
		#define ADF_DH895XCC_AE_MISC_CONTROL(i) (i * 0x1000 + 0x20960)
		#define ADF_DH895XCC_ENABLE_AE_ECC_ERR (1 << 28)
		#define ADF_DH895XCC_ENABLE_AE_ECC_PARITY_CORR (1 << 24 \| 1 << 12)
		#define ADF_DH895XCC_UERRSSMSH(i) (i * 0x4000 + 0x18)
		#define ADF_DH895XCC_CERRSSMSH(i) (i * 0x4000 + 0x10)
		#define ADF_DH895XCC_ERRSSMSH_EN (1 << 3)

		/* Admin Messages Registers */
		#define ADF_DH895XCC_ADMINMSGUR_OFFSET (0x3A000 + 0x574)
		#define ADF_DH895XCC_ADMINMSGLR_OFFSET (0x3A000 + 0x578)
		#define ADF_DH895XCC_MAILBOX_BASE_OFFSET 0x20970
		#define ADF_DH895XCC_MAILBOX_STRIDE 0x1000
		#define ADF_DH895XCC_FW "qat_895xcc.bin"
		#endif

drivers/crypto/qat/qat_dh895xcc/adf_drv.c

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