powerpc: Remove Xilinx PPC405/PPC440 support (7ade8495) · Commits · 戴 / test

Documentation/devicetree/bindings/xilinx.txt

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		@@ -86,149 +86,6 @@
		xlnx,use-parity = <0>;
		};

		Some IP cores actually implement 2 or more logical devices. In
		this case, the device should still describe the whole IP core with
		a single node and add a child node for each logical device. The
		ranges property can be used to translate from parent IP-core to the
		registers of each device. In addition, the parent node should be
		compatible with the bus type 'xlnx,compound', and should contain
		#address-cells and #size-cells, as with any other bus. (Note: this
		makes the assumption that both logical devices have the same bus
		binding. If this is not true, then separate nodes should be used
		for each logical device). The 'cell-index' property can be used to
		enumerate logical devices within an IP core. For example, the
		following is the system.mhs entry for the dual ps2 controller found
		on the ml403 reference design.

		BEGIN opb_ps2_dual_ref
		PARAMETER INSTANCE = opb_ps2_dual_ref_0
		PARAMETER HW_VER = 1.00.a
		PARAMETER C_BASEADDR = 0xA9000000
		PARAMETER C_HIGHADDR = 0xA9001FFF
		BUS_INTERFACE SOPB = opb_v20_0
		PORT Sys_Intr1 = ps2_1_intr
		PORT Sys_Intr2 = ps2_2_intr
		PORT Clkin1 = ps2_clk_rx_1
		PORT Clkin2 = ps2_clk_rx_2
		PORT Clkpd1 = ps2_clk_tx_1
		PORT Clkpd2 = ps2_clk_tx_2
		PORT Rx1 = ps2_d_rx_1
		PORT Rx2 = ps2_d_rx_2
		PORT Txpd1 = ps2_d_tx_1
		PORT Txpd2 = ps2_d_tx_2
		END

		It would result in the following device tree nodes:

		opb_ps2_dual_ref_0: opb-ps2-dual-ref@a9000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "xlnx,compound";
		ranges = <0 a9000000 2000>;
		// If this device had extra parameters, then they would
		// go here.
		ps2@0 {
		compatible = "xlnx,opb-ps2-dual-ref-1.00.a";
		reg = <0 40>;
		interrupt-parent = <&opb_intc_0>;
		interrupts = <3 0>;
		cell-index = <0>;
		};
		ps2@1000 {
		compatible = "xlnx,opb-ps2-dual-ref-1.00.a";
		reg = <1000 40>;
		interrupt-parent = <&opb_intc_0>;
		interrupts = <3 0>;
		cell-index = <0>;
		};
		};

		Also, the system.mhs file defines bus attachments from the processor
		to the devices. The device tree structure should reflect the bus
		attachments. Again an example; this system.mhs fragment:

		BEGIN ppc405_virtex4
		PARAMETER INSTANCE = ppc405_0
		PARAMETER HW_VER = 1.01.a
		BUS_INTERFACE DPLB = plb_v34_0
		BUS_INTERFACE IPLB = plb_v34_0
		END

		BEGIN opb_intc
		PARAMETER INSTANCE = opb_intc_0
		PARAMETER HW_VER = 1.00.c
		PARAMETER C_BASEADDR = 0xD1000FC0
		PARAMETER C_HIGHADDR = 0xD1000FDF
		BUS_INTERFACE SOPB = opb_v20_0
		END

		BEGIN opb_uart16550
		PARAMETER INSTANCE = opb_uart16550_0
		PARAMETER HW_VER = 1.00.d
		PARAMETER C_BASEADDR = 0xa0000000
		PARAMETER C_HIGHADDR = 0xa0001FFF
		BUS_INTERFACE SOPB = opb_v20_0
		END

		BEGIN plb_v34
		PARAMETER INSTANCE = plb_v34_0
		PARAMETER HW_VER = 1.02.a
		END

		BEGIN plb_bram_if_cntlr
		PARAMETER INSTANCE = plb_bram_if_cntlr_0
		PARAMETER HW_VER = 1.00.b
		PARAMETER C_BASEADDR = 0xFFFF0000
		PARAMETER C_HIGHADDR = 0xFFFFFFFF
		BUS_INTERFACE SPLB = plb_v34_0
		END

		BEGIN plb2opb_bridge
		PARAMETER INSTANCE = plb2opb_bridge_0
		PARAMETER HW_VER = 1.01.a
		PARAMETER C_RNG0_BASEADDR = 0x20000000
		PARAMETER C_RNG0_HIGHADDR = 0x3FFFFFFF
		PARAMETER C_RNG1_BASEADDR = 0x60000000
		PARAMETER C_RNG1_HIGHADDR = 0x7FFFFFFF
		PARAMETER C_RNG2_BASEADDR = 0x80000000
		PARAMETER C_RNG2_HIGHADDR = 0xBFFFFFFF
		PARAMETER C_RNG3_BASEADDR = 0xC0000000
		PARAMETER C_RNG3_HIGHADDR = 0xDFFFFFFF
		BUS_INTERFACE SPLB = plb_v34_0
		BUS_INTERFACE MOPB = opb_v20_0
		END

		Gives this device tree (some properties removed for clarity):

		plb@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "xlnx,plb-v34-1.02.a";
		device_type = "ibm,plb";
		ranges; // 1:1 translation

		plb_bram_if_cntrl_0: bram@ffff0000 {
		reg = <ffff0000 10000>;
		}

		opb@20000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <20000000 20000000 20000000
		60000000 60000000 20000000
		80000000 80000000 40000000
		c0000000 c0000000 20000000>;

		opb_uart16550_0: serial@a0000000 {
		reg = <a00000000 2000>;
		};

		opb_intc_0: interrupt-controller@d1000fc0 {
		reg = <d1000fc0 20>;
		};
		};
		};

		That covers the general approach to binding xilinx IP cores into the
		device tree. The following are bindings for specific devices:

Documentation/powerpc/bootwrapper.rst

+2 −26

Original line number	Diff line number	Diff line
		@@ -70,28 +70,6 @@ Currently, the following image format targets exist:
		kernel with this image type and it depends entirely on
		the embedded device tree for all information.

		The simpleImage is useful for booting systems with
		an unknown firmware interface or for booting from
		a debugger when no firmware is present (such as on
		the Xilinx Virtex platform). The only assumption that
		simpleImage makes is that RAM is correctly initialized
		and that the MMU is either off or has RAM mapped to
		base address 0.

		simpleImage also supports inserting special platform
		specific initialization code to the start of the bootup
		sequence. The virtex405 platform uses this feature to
		ensure that the cache is invalidated before caching
		is enabled. Platform specific initialization code is
		added as part of the wrapper script and is keyed on
		the image target name. For example, all
		simpleImage.virtex405-* targets will add the
		virtex405-head.S initialization code (This also means
		that the dts file for virtex405 targets should be
		named (virtex405-<board>.dts). Search the wrapper
		script for 'virtex405' and see the file
		arch/powerpc/boot/virtex405-head.S for details.

		treeImage.%; Image format for used with OpenBIOS firmware found
		on some ppc4xx hardware. This image embeds a device
		tree blob inside the image.
		@@ -116,10 +94,8 @@ Image types which embed a device tree blob (simpleImage, dtbImage, treeImage,
		and cuImage) all generate the device tree blob from a file in the
		arch/powerpc/boot/dts/ directory. The Makefile selects the correct device
		tree source based on the name of the target. Therefore, if the kernel is
		built with 'make treeImage.walnut simpleImage.virtex405-ml403', then the
		build system will use arch/powerpc/boot/dts/walnut.dts to build
		treeImage.walnut and arch/powerpc/boot/dts/virtex405-ml403.dts to build
		the simpleImage.virtex405-ml403.
		built with 'make treeImage.walnut', then the build system will use
		arch/powerpc/boot/dts/walnut.dts to build treeImage.walnut.

		Two special targets called 'zImage' and 'zImage.initrd' also exist. These
		targets build all the default images as selected by the kernel configuration.

arch/powerpc/Kconfig.debug

+1 −1

Original line number	Diff line number	Diff line
		@@ -230,7 +230,7 @@ config PPC_EARLY_DEBUG_40x
		help
		Select this to enable early debugging for IBM 40x chips via the
		inbuilt serial port. This works on chips with a 16550 compatible
		UART. Xilinx chips with uartlite cannot use this option.
		UART.

		config PPC_EARLY_DEBUG_CPM
		bool "Early serial debugging for Freescale CPM-based serial ports"

arch/powerpc/boot/Makefile

+2 −5

Original line number	Diff line number	Diff line
		@@ -79,7 +79,6 @@ $(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405
		$(obj)/treeboot-iss4xx.o: BOOTCFLAGS += -mcpu=405
		$(obj)/treeboot-currituck.o: BOOTCFLAGS += -mcpu=405
		$(obj)/treeboot-akebono.o: BOOTCFLAGS += -mcpu=405
		$(obj)/virtex405-head.o: BOOTAFLAGS += -mcpu=405

		# The pre-boot decompressors pull in a lot of kernel headers and other source
		# files. This creates a bit of a dependency headache since we need to copy
		@@ -129,14 +128,12 @@ src-wlib-$(CONFIG_44x) += 4xx.c ebony.c bamboo.c
		src-wlib-$(CONFIG_PPC_8xx) += mpc8xx.c planetcore.c fsl-soc.c
		src-wlib-$(CONFIG_PPC_82xx) += pq2.c fsl-soc.c planetcore.c
		src-wlib-$(CONFIG_EMBEDDED6xx) += ugecon.c fsl-soc.c
		src-wlib-$(CONFIG_XILINX_VIRTEX) += uartlite.c
		src-wlib-$(CONFIG_CPM) += cpm-serial.c

		src-plat-y := of.c epapr.c
		src-plat-$(CONFIG_40x) += fixed-head.S ep405.c cuboot-hotfoot.c \
		treeboot-walnut.c cuboot-acadia.c \
		cuboot-kilauea.c simpleboot.c \
		virtex405-head.S virtex.c
		cuboot-kilauea.c simpleboot.c
		src-plat-$(CONFIG_44x) += treeboot-ebony.c cuboot-ebony.c treeboot-bamboo.c \
		cuboot-bamboo.c cuboot-sam440ep.c \
		cuboot-sequoia.c cuboot-rainier.c \
		@@ -144,7 +141,7 @@ src-plat-$(CONFIG_44x) += treeboot-ebony.c cuboot-ebony.c treeboot-bamboo.c \
		cuboot-warp.c cuboot-yosemite.c \
		treeboot-iss4xx.c treeboot-currituck.c \
		treeboot-akebono.c \
		simpleboot.c fixed-head.S virtex.c
		simpleboot.c fixed-head.S
		src-plat-$(CONFIG_PPC_8xx) += cuboot-8xx.c fixed-head.S ep88xc.c redboot-8xx.c
		src-plat-$(CONFIG_PPC_MPC52xx) += cuboot-52xx.c
		src-plat-$(CONFIG_PPC_82xx) += cuboot-pq2.c fixed-head.S ep8248e.c cuboot-824x.c

arch/powerpc/boot/dts/Makefile

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Original line number	Diff line number	Diff line
		@@ -4,4 +4,3 @@ subdir-y += fsl

		dtstree := $(srctree)/$(src)
		dtb-$(CONFIG_OF_ALL_DTBS) := $(patsubst $(dtstree)/%.dts,%.dtb, $(wildcard $(dtstree)/*.dts))
		dtb-$(CONFIG_XILINX_VIRTEX440_GENERIC_BOARD) += virtex440-ml507.dtb virtex440-ml510.dtb

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