Commit 7ade67b5 authored Nov 04, 2013 by Marc Zyngier Committed by Catalin Marinas Nov 04, 2013

arm64: move enabling of GIC before CPUs are set online



Commit 53ae3acd (arm64: Only enable local interrupts after the CPU
is marked online) moved the enabling of the GIC after the CPUs are
marked online.

This has some interesting effect:
[...]
[<ffffffc0002eefd8>] gic_raise_softirq+0xf8/0x160
[<ffffffc000088f58>] smp_send_reschedule+0x38/0x40
[<ffffffc0000c8728>] resched_task+0x84/0xc0
[<ffffffc0000c8cdc>] check_preempt_curr+0x58/0x98
[<ffffffc0000c8d38>] ttwu_do_wakeup+0x1c/0xf4
[<ffffffc0000c8f90>] ttwu_do_activate.constprop.84+0x64/0x70
[<ffffffc0000cad30>] try_to_wake_up+0x1d4/0x2b4
[<ffffffc0000cae6c>] default_wake_function+0x10/0x18
[<ffffffc0000c5ca4>] __wake_up_common+0x60/0xa0
[<ffffffc0000c7784>] complete+0x48/0x64
[<ffffffc000088bec>] secondary_start_kernel+0xe8/0x110
[...]

Here, we end-up calling gic_raise_softirq without having initialized
the interrupt controller for this CPU. While this goes unnoticed
with GICv2 (the distributor is always accessible), it explodes with
GICv3.

The fix is to move the call to notify_cpu_starting before we set
the secondary CPU online.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

parent 3c620626

arch/arm64/kernel/smp.c

+5 −5

Original line number	Diff line number	Diff line
		@@ -145,6 +145,11 @@ asmlinkage void secondary_start_kernel(void)
		if (cpu_ops[cpu]->cpu_postboot)
		cpu_ops[cpu]->cpu_postboot();

		/*
		* Enable GIC and timers.
		*/
		notify_cpu_starting(cpu);

		/*
		* OK, now it's safe to let the boot CPU continue. Wait for
		* the CPU migration code to notice that the CPU is online
		@@ -153,11 +158,6 @@ asmlinkage void secondary_start_kernel(void)
		set_cpu_online(cpu, true);
		complete(&cpu_running);

		/*
		* Enable GIC and timers.
		*/
		notify_cpu_starting(cpu);

		local_irq_enable();
		local_fiq_enable();

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