Merge tag 'drm-intel-fixes-2020-06-18' of...

static void

tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock,

				u32 level)

				u32 level, enum intel_output_type type)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);

	const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations;

	u32 n_entries, val, ln, dpcnt_mask, dpcnt_val;

	if (encoder->type == INTEL_OUTPUT_HDMI) {

	if (type == INTEL_OUTPUT_HDMI) {

		n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans);

		ddi_translations = tgl_dkl_phy_hdmi_ddi_trans;

	} else {

	if (intel_phy_is_combo(dev_priv, phy))

		icl_combo_phy_ddi_vswing_sequence(encoder, level, type);

	else

		tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level);

		tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level, type);

}

static u32 translate_signal_level(struct intel_dp *intel_dp, int signal_levels)

		ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port));

	}

	ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X1_MODE);

	ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);

	ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);

	/* DPPATC */

					  INTEL_OUTPUT_DP_MST);

	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);

	intel_dp_set_infoframes(encoder, false, old_crtc_state, old_conn_state);

	if (!is_mst)

		intel_dp_set_infoframes(encoder, false,

					old_crtc_state, old_conn_state);

	/*

	 * Power down sink before disabling the port, otherwise we end

	 */

	drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port,

				     false);

	/*

	 * BSpec 4287: disable DIP after the transcoder is disabled and before

	 * the transcoder clock select is set to none.

	 */

	if (last_mst_stream)

		intel_dp_set_infoframes(&intel_dig_port->base, false,

					old_crtc_state, NULL);

	/*

	 * From TGL spec: "If multi-stream slave transcoder: Configure

	 * Transcoder Clock Select to direct no clock to the transcoder"

struct measure_breadcrumb {

	struct i915_request rq;

	struct intel_ring ring;

	u32 cs[1024];

	u32 cs[2048];

};

static int measure_breadcrumb_dw(struct intel_context *ce)

	frame->ring.vaddr = frame->cs;

	frame->ring.size = sizeof(frame->cs);

	frame->ring.wrap =

		BITS_PER_TYPE(frame->ring.size) - ilog2(frame->ring.size);

	frame->ring.effective_size = frame->ring.size;

	intel_ring_update_space(&frame->ring);

	frame->rq.ring = &frame->ring;

			list_move(&rq->sched.link, pl);

			set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);

			/* Check in case we rollback so far we wrap [size/2] */

			if (intel_ring_direction(rq->ring,

						 intel_ring_wrap(rq->ring,

								 rq->tail),

						 rq->ring->tail) > 0)

				rq->context->lrc.desc |= CTX_DESC_FORCE_RESTORE;

			active = rq;

		} else {

			struct intel_engine_cs *owner = rq->context->engine;

	 * HW has a tendency to ignore us rewinding the TAIL to the end of

	 * an earlier request.

	 */

	GEM_BUG_ON(ce->lrc_reg_state[CTX_RING_TAIL] != rq->ring->tail);

	prev = rq->ring->tail;

	tail = intel_ring_set_tail(rq->ring, rq->tail);

	prev = ce->lrc_reg_state[CTX_RING_TAIL];

	if (unlikely(intel_ring_direction(rq->ring, tail, prev) <= 0))

		desc |= CTX_DESC_FORCE_RESTORE;

	ce->lrc_reg_state[CTX_RING_TAIL] = tail;

static bool

need_timeslice(const struct intel_engine_cs *engine,

	       const struct i915_request *rq)

	       const struct i915_request *rq,

	       const struct rb_node *rb)

{

	int hint;

		return false;

	hint = engine->execlists.queue_priority_hint;

	if (rb) {

		const struct virtual_engine *ve =

			rb_entry(rb, typeof(*ve), nodes[engine->id].rb);

		const struct intel_engine_cs *inflight =

			intel_context_inflight(&ve->context);

		if (!inflight || inflight == engine) {

			struct i915_request *next;

			rcu_read_lock();

			next = READ_ONCE(ve->request);

			if (next)

				hint = max(hint, rq_prio(next));

			rcu_read_unlock();

		}

	}

	if (!list_is_last(&rq->sched.link, &engine->active.requests))

		hint = max(hint, rq_prio(list_next_entry(rq, sched.link)));

	GEM_BUG_ON(hint >= I915_PRIORITY_UNPREEMPTABLE);

	return hint >= effective_prio(rq);

}

	set_timer_ms(&engine->execlists.timer, duration);

}

static void start_timeslice(struct intel_engine_cs *engine)

static void start_timeslice(struct intel_engine_cs *engine, int prio)

{

	struct intel_engine_execlists *execlists = &engine->execlists;

	const int prio = queue_prio(execlists);

	unsigned long duration;

	if (!intel_engine_has_timeslices(engine))

			__unwind_incomplete_requests(engine);

			last = NULL;

		} else if (need_timeslice(engine, last) &&

		} else if (need_timeslice(engine, last, rb) &&

			   timeslice_expired(execlists, last)) {

			if (i915_request_completed(last)) {

				tasklet_hi_schedule(&execlists->tasklet);

				 * Even if ELSP[1] is occupied and not worthy

				 * of timeslices, our queue might be.

				 */

				start_timeslice(engine);

				start_timeslice(engine, queue_prio(execlists));

				return;

			}

		}

			if (last && !can_merge_rq(last, rq)) {

				spin_unlock(&ve->base.active.lock);

				start_timeslice(engine);

				start_timeslice(engine, rq_prio(rq));

				return; /* leave this for another sibling */

			}

	return 0;

}

static void assert_request_valid(struct i915_request *rq)

{

	struct intel_ring *ring __maybe_unused = rq->ring;

	/* Can we unwind this request without appearing to go forwards? */

	GEM_BUG_ON(intel_ring_direction(ring, rq->wa_tail, rq->head) <= 0);

}

/*

 * Reserve space for 2 NOOPs at the end of each request to be

 * used as a workaround for not being allowed to do lite

	*cs++ = MI_NOOP;

	request->wa_tail = intel_ring_offset(request, cs);

	/* Check that entire request is less than half the ring */

	assert_request_valid(request);

	return cs;

}

	GEM_BUG_ON(rq->ring->emit & (CACHELINE_BYTES - 1));

	return 0;

}

#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)

#include "selftest_ring.c"

#endif