Commit 7aa908b4 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-renesas-for-v5.10-tag2' of... 

Merge tag 'clk-renesas-for-v5.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Add support for the new R-Car V3U (R8A779A0) SoC
 - Add support for the VSP for Resizing clock on RZ/G1H,
 - Fix VSP clock names to match corrected hardware documentation.
 - Minor fixes and improvements

* tag 'clk-renesas-for-v5.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: rcar-gen3: Update description for RZ/G2
  clk: renesas: cpg-mssr: Add support for R-Car V3U
  clk: renesas: cpg-mssr: Add register pointers into struct cpg_mssr_priv
  clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flag
  dt-bindings: clock: renesas,cpg-mssr: Document r8a779a0
  dt-bindings: clock: Add r8a779a0 CPG Core Clock Definitions
  dt-bindings: power: Add r8a779a0 SYSC power domain definitions
  clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
  clk: renesas: r8a7742: Add clk entry for VSPR
parents 9123e3a7 15d683e6

Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml

+1 −0
Original line number Diff line number Diff line
@@ -47,6 +47,7 @@ properties: 
      - renesas,r8a77980-cpg-mssr # R-Car V3H

      - renesas,r8a77990-cpg-mssr # R-Car E3

      - renesas,r8a77995-cpg-mssr # R-Car D3

      - renesas,r8a779a0-cpg-mssr # R-Car V3U



  reg:

    maxItems: 1

drivers/clk/renesas/Kconfig

+6 −1
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@ config CLK_RENESAS 
	select CLK_R8A77980 if ARCH_R8A77980

	select CLK_R8A77990 if ARCH_R8A77990

	select CLK_R8A77995 if ARCH_R8A77995

	select CLK_R8A779A0 if ARCH_R8A779A0

	select CLK_R9A06G032 if ARCH_R9A06G032

	select CLK_SH73A0 if ARCH_SH73A0
@@ -145,6 +146,10 @@ config CLK_R8A77995 
	bool "R-Car D3 clock support" if COMPILE_TEST

	select CLK_RCAR_GEN3_CPG



config CLK_R8A779A0

	bool "R-Car V3U clock support" if COMPILE_TEST

	select CLK_RENESAS_CPG_MSSR



config CLK_R9A06G032

	bool "Renesas R9A06G032 clock driver"

	help
@@ -162,7 +167,7 @@ config CLK_RCAR_GEN2_CPG 
	select CLK_RENESAS_CPG_MSSR



config CLK_RCAR_GEN3_CPG

	bool "R-Car Gen3 CPG clock support" if COMPILE_TEST

	bool "R-Car Gen3 and RZ/G2 CPG clock support" if COMPILE_TEST

	select CLK_RENESAS_CPG_MSSR



config CLK_RCAR_USB2_CLOCK_SEL

drivers/clk/renesas/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o 
obj-$(CONFIG_CLK_R8A77980)		+= r8a77980-cpg-mssr.o

obj-$(CONFIG_CLK_R8A77990)		+= r8a77990-cpg-mssr.o

obj-$(CONFIG_CLK_R8A77995)		+= r8a77995-cpg-mssr.o

obj-$(CONFIG_CLK_R8A779A0)		+= r8a779a0-cpg-mssr.o

obj-$(CONFIG_CLK_R9A06G032)		+= r9a06g032-clocks.o

obj-$(CONFIG_CLK_SH73A0)		+= clk-sh73a0.o

drivers/clk/renesas/r7s9210-cpg-mssr.c

+1 −1
Original line number Diff line number Diff line
@@ -214,7 +214,7 @@ const struct cpg_mssr_info r7s9210_cpg_mssr_info __initconst = { 
	.cpg_clk_register = rza2_cpg_clk_register,



	/* RZ/A2 has Standby Control Registers */

	.stbyctrl = true,

	.reg_layout = CLK_REG_LAYOUT_RZ_A,

};



static void __init r7s9210_cpg_mssr_early_init(struct device_node *np)

drivers/clk/renesas/r8a7742-cpg-mssr.c

+2 −1
Original line number Diff line number Diff line
@@ -97,7 +97,8 @@ static const struct mssr_mod_clk r8a7742_mod_clks[] __initconst = { 
	DEF_MOD("tmu0",			 125,	R8A7742_CLK_CP),

	DEF_MOD("vsp1du1",		 127,	R8A7742_CLK_ZS),

	DEF_MOD("vsp1du0",		 128,	R8A7742_CLK_ZS),

	DEF_MOD("vsp1-sy",		 131,	R8A7742_CLK_ZS),

	DEF_MOD("vspr",			 130,	R8A7742_CLK_ZS),

	DEF_MOD("vsps",			 131,	R8A7742_CLK_ZS),

	DEF_MOD("scifa2",		 202,	R8A7742_CLK_MP),

	DEF_MOD("scifa1",		 203,	R8A7742_CLK_MP),

	DEF_MOD("scifa0",		 204,	R8A7742_CLK_MP),

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