Commit 7a66647b authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Kishon Vijay Abraham I
Browse files

phy: exynos: Use one define for enable bit 



There is no need for separate defines for Exynos4 and Exynos5 phy enable
bit and MIPI phy reset bits.  In both cases there are the same so
simplify it.

This reduces number of defines and allows removal of one header file.

Signed-off-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
Acked-by: default avatarLee Jones <lee.jones@linaro.org>
Reviewed-by: default avatarBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
parent 33e9a6aa

drivers/phy/phy-exynos-dp-video.c

+2 −3
Original line number Diff line number Diff line
@@ -14,7 +14,6 @@ 
#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/mfd/syscon.h>

#include <linux/mfd/syscon/exynos5-pmu.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <linux/phy/phy.h>
@@ -37,7 +36,7 @@ static int exynos_dp_video_phy_power_on(struct phy *phy) 


	/* Disable power isolation on DP-PHY */

	return regmap_update_bits(state->regs, state->drvdata->phy_ctrl_offset,

				  EXYNOS5_PHY_ENABLE, EXYNOS5_PHY_ENABLE);

				  EXYNOS4_PHY_ENABLE, EXYNOS4_PHY_ENABLE);

}



static int exynos_dp_video_phy_power_off(struct phy *phy)
@@ -46,7 +45,7 @@ static int exynos_dp_video_phy_power_off(struct phy *phy) 


	/* Enable power isolation on DP-PHY */

	return regmap_update_bits(state->regs, state->drvdata->phy_ctrl_offset,

				  EXYNOS5_PHY_ENABLE, 0);

				  EXYNOS4_PHY_ENABLE, 0);

}



static const struct phy_ops exynos_dp_video_phy_ops = {

drivers/phy/phy-exynos-mipi-video.c

+19 −20
Original line number Diff line number Diff line
@@ -12,7 +12,6 @@ 
#include <linux/err.h>

#include <linux/io.h>

#include <linux/kernel.h>

#include <linux/mfd/syscon/exynos5-pmu.h>

#include <linux/module.h>

#include <linux/of.h>

#include <linux/of_address.h>
@@ -64,7 +63,7 @@ static const struct mipi_phy_device_desc s5pv210_mipi_phy = { 
		{

			/* EXYNOS_MIPI_PHY_ID_CSIS0 */

			.coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,

			.enable_val = EXYNOS4_MIPI_PHY_ENABLE,

			.enable_val = EXYNOS4_PHY_ENABLE,

			.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),

			.enable_map = EXYNOS_MIPI_REGMAP_PMU,

			.resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
@@ -73,7 +72,7 @@ static const struct mipi_phy_device_desc s5pv210_mipi_phy = { 
		}, {

			/* EXYNOS_MIPI_PHY_ID_DSIM0 */

			.coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,

			.enable_val = EXYNOS4_MIPI_PHY_ENABLE,

			.enable_val = EXYNOS4_PHY_ENABLE,

			.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),

			.enable_map = EXYNOS_MIPI_REGMAP_PMU,

			.resetn_val = EXYNOS4_MIPI_PHY_MRESETN,
@@ -82,7 +81,7 @@ static const struct mipi_phy_device_desc s5pv210_mipi_phy = { 
		}, {

			/* EXYNOS_MIPI_PHY_ID_CSIS1 */

			.coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM1,

			.enable_val = EXYNOS4_MIPI_PHY_ENABLE,

			.enable_val = EXYNOS4_PHY_ENABLE,

			.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),

			.enable_map = EXYNOS_MIPI_REGMAP_PMU,

			.resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
@@ -91,7 +90,7 @@ static const struct mipi_phy_device_desc s5pv210_mipi_phy = { 
		}, {

			/* EXYNOS_MIPI_PHY_ID_DSIM1 */

			.coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS1,

			.enable_val = EXYNOS4_MIPI_PHY_ENABLE,

			.enable_val = EXYNOS4_PHY_ENABLE,

			.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),

			.enable_map = EXYNOS_MIPI_REGMAP_PMU,

			.resetn_val = EXYNOS4_MIPI_PHY_MRESETN,
@@ -109,46 +108,46 @@ static const struct mipi_phy_device_desc exynos5420_mipi_phy = { 
		{

			/* EXYNOS_MIPI_PHY_ID_CSIS0 */

			.coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,

			.enable_val = EXYNOS5_PHY_ENABLE,

			.enable_val = EXYNOS4_PHY_ENABLE,

			.enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),

			.enable_map = EXYNOS_MIPI_REGMAP_PMU,

			.resetn_val = EXYNOS5_MIPI_PHY_S_RESETN,

			.resetn_val = EXYNOS4_MIPI_PHY_SRESETN,

			.resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),

			.resetn_map = EXYNOS_MIPI_REGMAP_PMU,

		}, {

			/* EXYNOS_MIPI_PHY_ID_DSIM0 */

			.coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,

			.enable_val = EXYNOS5_PHY_ENABLE,

			.enable_val = EXYNOS4_PHY_ENABLE,

			.enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),

			.enable_map = EXYNOS_MIPI_REGMAP_PMU,

			.resetn_val = EXYNOS5_MIPI_PHY_M_RESETN,

			.resetn_val = EXYNOS4_MIPI_PHY_MRESETN,

			.resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),

			.resetn_map = EXYNOS_MIPI_REGMAP_PMU,

		}, {

			/* EXYNOS_MIPI_PHY_ID_CSIS1 */

			.coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM1,

			.enable_val = EXYNOS5_PHY_ENABLE,

			.enable_val = EXYNOS4_PHY_ENABLE,

			.enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),

			.enable_map = EXYNOS_MIPI_REGMAP_PMU,

			.resetn_val = EXYNOS5_MIPI_PHY_S_RESETN,

			.resetn_val = EXYNOS4_MIPI_PHY_SRESETN,

			.resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),

			.resetn_map = EXYNOS_MIPI_REGMAP_PMU,

		}, {

			/* EXYNOS_MIPI_PHY_ID_DSIM1 */

			.coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS1,

			.enable_val = EXYNOS5_PHY_ENABLE,

			.enable_val = EXYNOS4_PHY_ENABLE,

			.enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),

			.enable_map = EXYNOS_MIPI_REGMAP_PMU,

			.resetn_val = EXYNOS5_MIPI_PHY_M_RESETN,

			.resetn_val = EXYNOS4_MIPI_PHY_MRESETN,

			.resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),

			.resetn_map = EXYNOS_MIPI_REGMAP_PMU,

		}, {

			/* EXYNOS_MIPI_PHY_ID_CSIS2 */

			.coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,

			.enable_val = EXYNOS5_PHY_ENABLE,

			.enable_val = EXYNOS4_PHY_ENABLE,

			.enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(2),

			.enable_map = EXYNOS_MIPI_REGMAP_PMU,

			.resetn_val = EXYNOS5_MIPI_PHY_S_RESETN,

			.resetn_val = EXYNOS4_MIPI_PHY_SRESETN,

			.resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(2),

			.resetn_map = EXYNOS_MIPI_REGMAP_PMU,

		},
@@ -172,7 +171,7 @@ static const struct mipi_phy_device_desc exynos5433_mipi_phy = { 
		{

			/* EXYNOS_MIPI_PHY_ID_CSIS0 */

			.coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,

			.enable_val = EXYNOS5_PHY_ENABLE,

			.enable_val = EXYNOS4_PHY_ENABLE,

			.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),

			.enable_map = EXYNOS_MIPI_REGMAP_PMU,

			.resetn_val = BIT(0),
@@ -181,7 +180,7 @@ static const struct mipi_phy_device_desc exynos5433_mipi_phy = { 
		}, {

			/* EXYNOS_MIPI_PHY_ID_DSIM0 */

			.coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,

			.enable_val = EXYNOS5_PHY_ENABLE,

			.enable_val = EXYNOS4_PHY_ENABLE,

			.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),

			.enable_map = EXYNOS_MIPI_REGMAP_PMU,

			.resetn_val = BIT(0),
@@ -190,7 +189,7 @@ static const struct mipi_phy_device_desc exynos5433_mipi_phy = { 
		}, {

			/* EXYNOS_MIPI_PHY_ID_CSIS1 */

			.coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,

			.enable_val = EXYNOS5_PHY_ENABLE,

			.enable_val = EXYNOS4_PHY_ENABLE,

			.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),

			.enable_map = EXYNOS_MIPI_REGMAP_PMU,

			.resetn_val = BIT(1),
@@ -199,7 +198,7 @@ static const struct mipi_phy_device_desc exynos5433_mipi_phy = { 
		}, {

			/* EXYNOS_MIPI_PHY_ID_DSIM1 */

			.coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,

			.enable_val = EXYNOS5_PHY_ENABLE,

			.enable_val = EXYNOS4_PHY_ENABLE,

			.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),

			.enable_map = EXYNOS_MIPI_REGMAP_PMU,

			.resetn_val = BIT(1),
@@ -208,7 +207,7 @@ static const struct mipi_phy_device_desc exynos5433_mipi_phy = { 
		}, {

			/* EXYNOS_MIPI_PHY_ID_CSIS2 */

			.coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,

			.enable_val = EXYNOS5_PHY_ENABLE,

			.enable_val = EXYNOS4_PHY_ENABLE,

			.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(2),

			.enable_map = EXYNOS_MIPI_REGMAP_PMU,

			.resetn_val = BIT(0),

drivers/phy/phy-exynos5-usbdrd.c

+2 −3
Original line number Diff line number Diff line
@@ -22,7 +22,6 @@ 
#include <linux/platform_device.h>

#include <linux/mutex.h>

#include <linux/mfd/syscon.h>

#include <linux/mfd/syscon/exynos5-pmu.h>

#include <linux/regmap.h>

#include <linux/regulator/consumer.h>

#include <linux/soc/samsung/exynos-regs-pmu.h>
@@ -236,10 +235,10 @@ static void exynos5_usbdrd_phy_isol(struct phy_usb_instance *inst, 
	if (!inst->reg_pmu)

		return;



	val = on ? 0 : EXYNOS5_PHY_ENABLE;

	val = on ? 0 : EXYNOS4_PHY_ENABLE;



	regmap_update_bits(inst->reg_pmu, inst->pmu_offset,

			   EXYNOS5_PHY_ENABLE, val);

			   EXYNOS4_PHY_ENABLE, val);

}



/*

include/linux/soc/samsung/exynos-regs-pmu.h

+2 −1
Original line number Diff line number Diff line
@@ -52,7 +52,8 @@ 


/* MIPI_PHYn_CONTROL, valid for Exynos3250, Exynos4, Exynos5250 and Exynos5433 */

#define EXYNOS4_MIPI_PHY_CONTROL(n)		(0x0710 + (n) * 4)

#define EXYNOS4_MIPI_PHY_ENABLE			(1 << 0)

/* Phy enable bit, common for all phy registers, not only MIPI */

#define EXYNOS4_PHY_ENABLE			(1 << 0)

#define EXYNOS4_MIPI_PHY_SRESETN		(1 << 1)

#define EXYNOS4_MIPI_PHY_MRESETN		(1 << 2)

#define EXYNOS4_MIPI_PHY_RESET_MASK		(3 << 1)

CRA Git | Maintained and supported by SUSTech CRA and CCSE