Commit 7a2852e4 authored by Thomas Bogendoerfer's avatar Thomas Bogendoerfer Committed by Ralf Baechle
Browse files

[MIPS] IP28: switch to "normal" mode after PROM no longer needed 



SGI-IP28 is running in so called slow mode, when kernel is started
from the PROM. PROM calls must be done in slow mode otherwise the
PROM will issue an error. To get better memory performance we now
switch to normal mode, when the PROM is no longer needed.

Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent c3dd3de7

arch/mips/sgi-ip22/ip22-mc.c

+26 −0
Original line number Diff line number Diff line
@@ -208,4 +208,30 @@ void __init sgimc_init(void) 
void __init prom_meminit(void) {}

void __init prom_free_prom_memory(void)

{

#ifdef CONFIG_SGI_IP28

	u32 mconfig1;

	unsigned long flags;

	spinlock_t lock;



	/*

	 * because ARCS accesses memory uncached we wait until ARCS

	 * isn't needed any longer, before we switch from slow to

	 * normal mode

	 */

	spin_lock_irqsave(&lock, flags);

	mconfig1 = sgimc->mconfig1;

	/* map ECC register */

	sgimc->mconfig1 = (mconfig1 & 0xffff0000) | 0x2060;

	iob();

	/* switch to normal mode */

	*(unsigned long *)PHYS_TO_XKSEG_UNCACHED(0x60000000) = 0;

	iob();

	/* reduce WR_COL */

	sgimc->cmacc = (sgimc->cmacc & ~0xf) | 4;

	iob();

	/* restore old config */

	sgimc->mconfig1 = mconfig1;

	iob();

	spin_unlock_irqrestore(&lock, flags);

#endif

}

include/asm-mips/barrier.h

+14 −0
Original line number Diff line number Diff line
@@ -92,11 +92,25 @@ 
#define fast_wmb()	__sync()

#define fast_rmb()	__sync()

#define fast_mb()	__sync()

#ifdef CONFIG_SGI_IP28

#define fast_iob()				\

	__asm__ __volatile__(			\

		".set	push\n\t"		\

		".set	noreorder\n\t"		\

		"lw	$0,%0\n\t"		\

		"sync\n\t"			\

		"lw	$0,%0\n\t"		\

		".set	pop"			\

		: /* no output */		\

		: "m" (*(int *)CKSEG1ADDR(0x1fa00004)) \

		: "memory")

#else

#define fast_iob()				\

	do {					\

		__sync();			\

		__fast_iob();			\

	} while (0)

#endif



#ifdef CONFIG_CPU_HAS_WB

CRA Git | Maintained and supported by SUSTech CRA and CCSE