Commit 7a1b29a8 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile 

* git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile:
  arch/tile: don't validate CROSS_COMPILE needlessly
  arch/tile: export only COMMAND_LINE_SIZE to userspace.
  arch/tile: rename ARCH_KMALLOC_MINALIGN to ARCH_DMA_MINALIGN
  arch/tile: Rename the hweight() implementations to __arch_hweight()
  arch/tile: extend syscall ABI to set r1 on return as well.
  arch/tile: Various cleanups.
  arch/tile: support backtracing on TILE-Gx
  arch/tile: Fix a couple of issues with the COMPAT code for TILE-Gx.
  arch/tile: Use separate, better minsec values for clocksource and sched_clock.
  arch/tile: correct a bug in freeing bootmem by VA for the optional second initrd.
  arch: tile: mm: pgtable.c: Removed duplicated #include
  arch: tile: kernel/proc.c Removed duplicated #include
  Add fanotify syscalls to <asm-generic/unistd.h>.
  arch/tile: support new kunmap_atomic() naming convention.
  tile: remove unused ISA_DMA_THRESHOLD define

Conflicts in arch/tile/configs/tile_defconfig (pick the mainline version
with the reduced defconfig).
parents d7824370 a5854dd7

arch/tile/Makefile

+11 −9
Original line number Diff line number Diff line
@@ -8,21 +8,23 @@ 
# for "archclean" and "archdep" for cleaning up and making dependencies for

# this architecture



ifeq ($(CROSS_COMPILE),)

# If building with TILERA_ROOT set (i.e. using the Tilera Multicore

# Development Environment) we can set CROSS_COMPILE based on that.

ifdef TILERA_ROOT

CROSS_COMPILE	= $(TILERA_ROOT)/bin/tile-

endif

endif



# If we're not cross-compiling, make sure we're on the right architecture.

# Only bother to test for a few common targets, to avoid useless errors.

ifeq ($(CROSS_COMPILE),)

HOST_ARCH = $(shell uname -m)

  ifdef TILERA_ROOT

    CROSS_COMPILE := $(TILERA_ROOT)/bin/tile-

  else

    goals := $(if $(MAKECMDGOALS), $(MAKECMDGOALS), all)

    ifneq ($(strip $(filter vmlinux modules all,$(goals))),)

      HOST_ARCH := $(shell uname -m)

      ifneq ($(HOST_ARCH),$(ARCH))

$(error Set TILERA_ROOT or CROSS_COMPILE when building $(ARCH) on $(HOST_ARCH))

      endif

    endif

  endif

endif





KBUILD_CFLAGS   += $(CONFIG_DEBUG_EXTRA_FLAGS)

arch/tile/include/arch/abi.h

+1 −3
Original line number Diff line number Diff line
@@ -59,9 +59,7 @@ 
 * The ABI requires callers to allocate a caller state save area of

 * this many bytes at the bottom of each stack frame.

 */

#ifdef __tile__

#define C_ABI_SAVE_AREA_SIZE (2 * __SIZEOF_POINTER__)

#endif

#define C_ABI_SAVE_AREA_SIZE (2 * (CHIP_WORD_SIZE() / 8))



/**

 * The operand to an 'info' opcode directing the backtracer to not

arch/tile/include/asm/atomic_32.h

+0 −37
Original line number Diff line number Diff line
@@ -255,43 +255,6 @@ static inline void atomic64_set(atomic64_t *v, u64 n) 
#define smp_mb__after_atomic_dec()	do { } while (0)

#define smp_mb__after_atomic_inc()	do { } while (0)





/*

 * Support "tns" atomic integers.  These are atomic integers that can

 * hold any value but "1".  They are more efficient than regular atomic

 * operations because the "lock" (aka acquire) step is a single "tns"

 * in the uncontended case, and the "unlock" (aka release) step is a

 * single "store" without an mf.  (However, note that on tilepro the

 * "tns" will evict the local cache line, so it's not all upside.)

 *

 * Note that you can ONLY observe the value stored in the pointer

 * using these operations; a direct read of the value may confusingly

 * return the special value "1".

 */



int __tns_atomic_acquire(atomic_t *);

void __tns_atomic_release(atomic_t *p, int v);



static inline void tns_atomic_set(atomic_t *v, int i)

{

	__tns_atomic_acquire(v);

	__tns_atomic_release(v, i);

}



static inline int tns_atomic_cmpxchg(atomic_t *v, int o, int n)

{

	int ret = __tns_atomic_acquire(v);

	__tns_atomic_release(v, (ret == o) ? n : ret);

	return ret;

}



static inline int tns_atomic_xchg(atomic_t *v, int n)

{

	int ret = __tns_atomic_acquire(v);

	__tns_atomic_release(v, n);

	return ret;

}



#endif /* !__ASSEMBLY__ */



/*

arch/tile/include/asm/backtrace.h

+3 −1
Original line number Diff line number Diff line
@@ -21,7 +21,9 @@ 


#include <arch/chip.h>



#if CHIP_VA_WIDTH() > 32

#if defined(__tile__)

typedef unsigned long VirtualAddress;

#elif CHIP_VA_WIDTH() > 32

typedef unsigned long long VirtualAddress;

#else

typedef unsigned int VirtualAddress;

arch/tile/include/asm/bitops.h

+5 −4
Original line number Diff line number Diff line
@@ -98,26 +98,27 @@ static inline int fls64(__u64 w) 
	return (sizeof(__u64) * 8) - __builtin_clzll(w);

}



static inline unsigned int hweight32(unsigned int w)

static inline unsigned int __arch_hweight32(unsigned int w)

{

	return __builtin_popcount(w);

}



static inline unsigned int hweight16(unsigned int w)

static inline unsigned int __arch_hweight16(unsigned int w)

{

	return __builtin_popcount(w & 0xffff);

}



static inline unsigned int hweight8(unsigned int w)

static inline unsigned int __arch_hweight8(unsigned int w)

{

	return __builtin_popcount(w & 0xff);

}



static inline unsigned long hweight64(__u64 w)

static inline unsigned long __arch_hweight64(__u64 w)

{

	return __builtin_popcountll(w);

}



#include <asm-generic/bitops/const_hweight.h>

#include <asm-generic/bitops/lock.h>

#include <asm-generic/bitops/sched.h>

#include <asm-generic/bitops/ext2-non-atomic.h>

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