dt-bindings: interconnect: Add OSM L3 DT bindings

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/interconnect/qcom,osm-l3.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Operating State Manager (OSM) L3 Interconnect Provider

maintainers:

  - Sibi Sankar <sibis@codeaurora.org>

description:

  L3 cache bandwidth requirements on Qualcomm SoCs is serviced by the OSM.

  The OSM L3 interconnect provider aggregates the L3 bandwidth requests

  from CPU/GPU and relays it to the OSM.

properties:

  compatible:

    enum:

      - qcom,sdm845-osm-l3

  reg:

    maxItems: 1

  clocks:

    items:

      - description: xo clock

      - description: alternate clock

  clock-names:

    items:

      - const: xo

      - const: alternate

  '#interconnect-cells':

    const: 1

required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#interconnect-cells'

additionalProperties: false

examples:

  - |

    #define GPLL0               165

    #define RPMH_CXO_CLK        0

    osm_l3: interconnect@17d41000 {

      compatible = "qcom,sdm845-osm-l3";

      reg = <0x17d41000 0x1400>;

      clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;

      clock-names = "xo", "alternate";

      #interconnect-cells = <1>;

    };

/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (C) 2019 The Linux Foundation. All rights reserved.

 */

#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H

#define __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H

#define MASTER_OSM_L3_APPS	0

#define SLAVE_OSM_L3		1

#endif